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Design Automation for Embedded Systems, Volume 15
Volume 15, Number 1, March 2011
- Nadav Rotem, Yosi Ben-Asher:
Combining static and dynamic array detection for binary synthesis with multiple memory ports. 1-18 - Mohamed B. Abdelhalim
, Serag E.-D. Habib:
An integrated high-level hardware/software partitioning methodology. 19-50 - Olivier Morandi, Fulvio Risso
Creating portable and efficient packet processing applications. 51-85
Volume 15, Number 2, June 2011
- Kees Goossens, Radu Marculescu
Special Issue on Networks-on-Chips: Design Flows and Case Studies. 87-88 - Dongkun Shin, Woojoong Kim, Soontae Kwon, Tae Hee Han
Communication-aware VFI partitioning for GALS-based networks-on-chip. 89-109 - Kun-Chih Chen
A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks. 111-132 - Jean-Jacques Lecler, Gilles Baillieu:
Application driven network-on-chip architecture exploration & refinement for a complex SoC. 133-158 - Andreas Hansson, Kees Goossens:
A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications. 159-190
Volume 15, Numbers 3-4, December 2011
- Se Jin Kwon
FTL algorithms for NAND-type flash memories. 191-224 - Cássio L. Rodrigues, Karina R. G. da Silva, Henrique do N. Cunha, Jorge C. A. de Figueiredo, Dalton Dario Serey Guerrero, Elmar U. K. Melcher:
Enhancing IP cores specifications using hierarchical composition and set theory. 225-245 - Beniamin Apopei, Tony J. Dodd
FPGA automatic re-synchronisation for pipelined, floating point control systems applications. 247-288 - Mostafa Kishani
HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors. 289-310 - Hanno Scharwächter, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
A retargetable framework for compiler/architecture co-development. 311-342
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