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32nd SBCCI 2019: Sao Paulo, Brazil
- João Antonio Martino, Marcelo Lubaszewski, Matteo Sonza Reorda:
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, SBCCI 2019, Sao Paulo, Brazil, August 26-30, 2019. ACM 2019, ISBN 978-1-4503-6844-5 - Philippe de S. Magalhães, Otávio Alcântara de Lime Jr., Jarbas Silveira
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PHICC: an error correction code for memory devices. 1 - Anderson Camargo Sant'Ana, Henrique Martins Medina, Kevin Boucinha Fiorentin, Fernando Gehm Moraes
Lightweight security mechanisms for MPSoCs. 2 - Gennaro Severino Rodrigues, Juan Fonseca, Fabio Benevenuti, Fernanda Lima Kastensmidt, Alberto Bosio:
Exploiting approximate computing for low-cost fault tolerant architectures. 3 - Alzemiro Henrique Lucas da Silva, André Luís Del Mestre Martins, Fernando Gehm Moraes
Fine-grain temperature monitoring for many-core systems. 4 - Jessé Barreto de Barros, Renato Coral Sampaio, Carlos H. Llanos
An adaptive discrete particle swarm optimization for mapping real-time applications onto network-on-a-chip based MPSoCs. 5 - Guilherme Apolinario Silva Novaes, Luiz Carlos Moreira, Wang Jiang Chau:
Exploring Tabu search based algorithms for mapping and placement in NoC-based reconfigurable systems. 6 - Wagner Penny
Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms. 7 - Roberto Paulo Dias Alcantara Filho, Otávio Alcântara de Lima Júnior, Corneli Gomes Furtado Júnior:
An FPGA-based evaluation platform for energy harvesting embedded systems. 8 - Reneilson Santos, Edward David Moreno, Carlos A. Estombelo-Montesco:
A comparison of two embedded systems to detect electrical disturbances using decision tree algorithm. 9 - Willian de Assis Pedrobon Ferreira, Ian Andrew Grout, Alexandre César Rodrigues da Silva:
FPGA hardware linear regression implementation using fixed-point arithmetic. 10 - Adriana Arevalo, Romain Liautard, Daniel Romero, Lionel Trojman, Luis-Miguel Procel
New insight for next generation SRAM: tunnel FET versus FinFET for different topologies. 11 - Renan A. Marks
DNAr-logic: a constructive DNA logic circuit design library in R language for molecular computing. 12 - Alexandre A. A. de Almeida
Finding optimal qubit permutations for IBM's quantum computer architectures. 13 - Clement Raffaitin, Juan-Sebastian Romero, Luis-Miguel Procel
Hardware implementation of a shape recognition algorithm based on invariant moments. 14 - Guilherme A. M. Sborz, Guilherme A. Pohl, Felipe Viel
A custom processor for an FPGA-based platform for automatic license plate recognition. 15 - Jones Goebel, Bruno Zatt, Luciano Agostini, Marcelo Schiavon Porto:
Hardware design of DC/CFL intra-prediction decoder for the AV1 codec. 16 - Rafael da Silva, Ícaro Siqueira, Mateus Grellert
Approximate interpolation filters for the fractional motion estimation in HEVC encoders and their VLSI design. 17 - Lucas Amilton Martins, Guilherme A. M. Sborz, Felipe Viel
An SVM-based hardware accelerator for onboard classification of hyperspectral images. 18 - Arthur Liraneto Torres Costa, Hamilton Klimach, Sergio Bampi
A sub-1mA highly linear inductorless wideband LNA with low IP3 sensitivity to variability for IoT applications. 19 - Luis Schuartz
Comparison between direct and indirect learnings for the digital pre-distortion of concurrent dual-band power amplifiers. 20 - Rodrigo Alves De Lima Moreto, Douglas Rocha, Carlos E. Thomaz
Interactive evolutionary approach to reduce the optimization cycle time of a low noise amplifier. 21 - José Roberto Banin Júnior
An innovative strategy to reduce die area of robust OTA by using iMTGSPICE and diamond layout style for MOSFETs. 22 - Lucas A. Lascasas Freitas
NMLSim 2.0: a robust CAD and simulation tool for in-plane nanomagnetic logic based on the LLG equation. 23 - Ruan Evangelista Formigoni, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Ropper: a placement and routing framework for field-coupled nanotechnologies. 24 - Pedro Arthur R. L. Silva, Omar Paranaiba Vilela Neto
Toward nanometric scale integration: an automatic routing approach for NML circuits. 25 - Pietro M. Ferreira, Nathan De Carvalho, Geoffroy Klisnick, Aziz Benlarbi-Delaï:
Energy efficient fJ/spike LTS e-Neuron using 55-nm node. 26 - Antonio José Sobrinho de Sousa, Fabian Souza de Andrade, Hildeloi dos Santos, Gabriele Costa Goncalves, Maicon Deivid Pereira
CMOS analog four-quadrant multiplier free of voltage reference generators. 27 - Tiago Oliveira Weber
Amplifier-based MOS analog neural network implementation and weights optimization. 28 - Augusto Andre Souza Berndt, Alan Mishchenko, Paulo Francisco Butzen
Reduction of neural network circuits by constant and nearly constant signal propagation. 29 - Guilherme Korol, Fernando Gehm Moraes
A FPGA parameterizable multi-layer architecture for CNNs. 30 - Arthur Lombardi Campos
Design of a low power 10-bit 12MS/s asynchronous SAR ADC in 65nm CMOS. 31 - Li Huang, Caroline Lelandais-Perrault, Anthony Kolar
A new algorithm for an incremental sigma-delta converter reconstruction filter. 32 - Tales Luiz Bortolin, André Luiz Aita, João Baptista dos Santos Martins:
Behavioral modeling of a control module for an energy-investing piezoelectric harvester. 33 - Luiz Carlos Moreira, José Fontebasso Neto, Walter Silva Oliveira
An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process. 34
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