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ITC 2016: Fort Worth, TX, USA
- 2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016. IEEE 2016, ISBN 978-1-4673-8773-6
- Walden C. Rhines:
Plenary keynote address Tuesday: The business of test: Test and semiconductor economics. 9 - Rob A. Rutenbar:
Keynote address Wednesday: Hardware inference accelerators for machine learning. 10 - Ken Hansen:
Keynote address Thursday: Addressing semiconductor industry needs: Defining the future through creative, exciting research. 11 - M. Enamul Amyeen, Dongok Kim, Maheshwar Chandrasekar, Mohammad Noman, Srikanth Venkataraman, Anurag Jain, Neha Goel, Ramesh Sharma:
A novel diagnostic test generation methodology and its application in production failure isolation. 1-10 - Subhadip Kundu, Parthajit Bhattacharya, Rohit Kapur:
Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors. 1-7 - Kamran Saleem, Nur A. Touba:
Using symbolic canceling to improve diagnosis from compacted response. 1-7 - Carlston Lim, Yang Xue, Xin Li, Ronald D. Blanton, M. Enamul Amyeen:
Diagnostic resolution improvement through learning-guided physical failure analysis. 1-10 - Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer:
Minimal area test points for deterministic patterns. 1-7 - Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada:
Test point insertion in hybrid test compression/LBIST architectures. 1-10 - Dong Xiang, Krishnendu Chakrabarty
, Hideo Fujiwara:
A unified test and fault-tolerant multicast solution for network-on-chip designs. 1-9 - Fanchen Zhang, Daphne Hwong, Yi Sun, Allison Garcia, Soha Alhelaly, Geoff Shofner, LeRoy Winemberg, Jennifer Dworak:
Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture. 1-10 - Wim Dobbelaere, Ronny Vanhooren, Willy De Man, Koen Matthijs, Anthony Coyette, Baris Esen, Georges G. E. Gielen
Analog fault coverage improvement using final-test dynamic part average testing. 1-9 - Baris Esen, Anthony Coyette, Georges G. E. Gielen
Effective DC fault models and testing approach for open defects in analog circuits. 1-9 - Jyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary:
Fault simulation for analog test coverage. 1-7 - Chih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits. 1-7 - Tianjian Li, Li Jiang, Xiaoyao Liang, Qiang Xu
Defect tolerance for CNFET-based SRAMs. 1-9 - Insik Yoon, Ashwin Chintaluri, Arijit Raychowdhury:
EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays. 1-10 - Ali Ahmadi, Constantinos Xanthopoulos, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris
Harnessing process variations for optimizing wafer-level probe-test flow. 1-8 - Shi Jin, Zhaobo Zhang, Krishnendu Chakrabarty
Accurate anomaly detection using correlation-based time-series analysis in a core router system. 1-10 - David Shaw, Dirk Hoops, Kenneth M. Butler, Amit Nahar:
Statistical outlier screening as a test solution health monitor. 1-10 - Farrokh Ghani Zadegan
Upper-bound computation for optimal retargeting in IEEE1687 networks. 1-10 - Michele Portolan
Accessing 1687 systems using arbitrary protocols. 1-9 - Anton Tsertov
A suite of IEEE 1687 benchmark networks. 1-10 - Shalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi:
SERDES external loopback test using production parametric-test hardware. 1-7 - Y. Fan, A. Verma, Y. Su, L. Rose, J. Janney, V. Do, S. Kumar:
RF test accuracy and capacity enhancement on ATE for silicon TV tuners. 1-10 - Yuming Zhuang
Low cost ultra-pure sine wave generation with self calibration. 1-9 - Kenneth M. Butler, Amit Nahar, W. Robert Daasch:
What we know after twelve years developing and deploying test data analytics solutions. 1-8 - Chun-Kai Hsu, Peter Sarson, Gregor Schatzberger, Friedrich Peter Leisenberger, John M. Carulli Jr., Siddhartha Siddhartha, Kwang-Ting Cheng
Variation and failure characterization through pattern classification of test data from multiple test stages. 1-10 - Gurunath Kadam
Supply-voltage optimization to account for process variations in high-volume manufacturing testing. 1-9 - Zipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips. 1-10 - Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng:
Online slack-time binning for IO-registered die-to-die interconnects. 1-8 - Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal
Logic characterization vehicle design reflection via layout rewiring. 1-10 - Soumya Mittal
Test chip design for optimal cell-aware diagnosability. 1-8 - Dave Armstrong, Gary Maier:
Known-good-die test methods for large, thin, high-power digital devices. 1-6 - Gordon W. Roberts:
Mixed-signal ATE technology and its impact on today's electronic system. 1-7 - Peter Sarson:
Test time efficient group delay filter characterization technique using a discrete chirped excitation signal. 1-6 - Md. Mahbub Alam, Mark M. Tehranipoor, Domenic Forte
Recycled FPGA detection using exhaustive LUT path delay characterization. 1-10 - Anastasis Keliris, Hossein Salehghaffari, Brian R. Cairl, Prashanth Krishnamurthy, Michail Maniatakos
Machine learning-based defense against process-aware attacks on Industrial Control Systems. 1-10 - Jack Tang, Ramesh Karri
Securing digital microfluidic biochips by randomizing checkpoints. 1-8 - Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian:
Advanced test methodology for complex SoCs. 1-10 - Masahiro Murakami, Haruo Kobayashi, Shaiful Nizam Bin Mohyar
I-Q signal generation techniques for communication IC testing and ATE systems. 1-10 - Takayuki Nakamura, Koji Asami:
Novel crosstalk evaluation method for high-density signal traces using clock waveform conversion technique. 1-7 - Toru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada:
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board. 1-8 - Suvadeep Banerjee
Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states. 1-10 - Mehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark M. Tehranipoor:
BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning. 1-10 - Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González
Cross-layer system reliability assessment framework for hardware faults. 1-10 - Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li
An accurate algorithm for computing mutation coverage in model checking. 1-10 - Kuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte:
An on-chip self-test architecture with test patterns recorded in scan chains. 1-10 - Cheng-Hung Wu, Kuen-Jong Lee:
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement. 1-10 - Anthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen
Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis. 1-10 - Barry John Muldrey
DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems. 1-10 - Stephen Sunter, Alessandro Valerio, Riccardo Miglierina:
Automated measurement of defect tolerance in mixed-signal ICs. 1-8 - V. R. Devanathan, Sumant Kale:
A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath. 1-6 - Michael Johnson, Brian Noble, Mark Johnson, Jim Crafts, Cynthia Manya, John Deforge:
Active reliability monitor: Defect level extrinsic reliability monitoring on 22nm POWER8 and zSeries processors. 1-8 - Yan Pan, Rao Desineni, Kannan Sekar, Atul Chittora, Sherwin Fernandes, Neerja Bawaskar, John M. Carulli:
Pylon: Towards an integrated customizable volume diagnosis infrastructure. 1-9 - Wei-Cheng Lien
Output bit selection methodology for test response compaction. 1-10 - Panagiota Papavramidou:
Memory repair for high fault rates. 1-10 - Ran Wang, Krishnendu Chakrabarty
Testing of interposer-based 2.5D integrated circuits. 1-10
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