default search action
12th ICS 1998: Melbourne, Australia
- Greg K. Egan, Richard P. Brent, Dennis Gannon:
Proceedings of the 12th international conference on Supercomputing, ICS 1998, Melbourne, Australia, July 13-17, 1998. ACM 1998, ISBN 0-89791-998-X
High Performance Numerical Libraries
- Markus Hegland, Michael R. Osborne:
Algorithms for Block Bidiagonal Systems on Vector and Parallel Computers. 1-6 - Peter Christen:
A Parallel Iterative Linear System Solver with Dynamic Load Balancing. 7-12 - Richard P. Brent, L. Grosz, David L. Harrar II, Markus Hegland, Margaret Kahn, G. Keating, G. Mercer, Ole Møller Nielsen, Michael R. Osborne, Bing Bing Zhou, M. Nakanishi:
Development of a Mathematical Subroutine Library for Fujitsu Vector Parallel Processors. 13-20
Architectural Resource Management
- José González, Antonio González:
The Potential of Data Value Speculation to Boost ILP. 21-28 - Bryan Black, Brian Mueller, Stephanie Postal, Ryan N. Rakvic, Noppanunt Utamaphethai, John Paul Shen:
Load Execution Latency Reduction. 29-36 - Luis Villa, Roger Espasa, Mateo Valero:
A Performance Study of Out-of-order Vector Architectures and Short Registers. 37-44
Sparse Computation and Data Layout
- Rong-Guey Chang, Tyng-Ruey Chuang, Jenq Kuen Lee:
Efficient Support of Parallel Sparse Computation for Array Intrinsic Functions of Fortran 90. 45-52 - David A. Koufaty, Josep Torrellas:
Comparing Data Forwarding and Prefetching for Communication-induced Misses in Shared-memory MPs. 53-60 - Dhruva R. Chakrabarti, U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee:
An Efficient Uniform Run-time Scheme for Mixed Regular-irregular Applications. 61-68 - Mahmut T. Kandemir, Alok N. Choudhary, U. Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam:
A Hyperplane Based Approach for Optimizing Spatial Locality in Loop Nests. 69-76
Speculative Execution
- Pedro Marcuello, Antonio González, Jordi Tubella:
Speculative Multithreaded Processors. 77-84 - Venkata Krishnan, Josep Torrellas:
Hardware and Software Support for Speculative Execution of Sequential Binaries on a Chip-multiprocessor. 85-92 - Iffat H. Kazi, David J. Lilja:
Coarse-grained Speculative Execution in Shared-memory Multiprocessors. 93-100 - Pritpal S. Ahuja, Kevin Skadron, Margaret Martonosi, Douglas W. Clark:
Multipath Execution: Opportunities and Limits. 101-108
Compilation Technology
- Siegfried Benkner, Piyush Mehrotra, John Van Rosendale, Hans P. Zima:
High-level Management of Communication Schedules in HPF-like Languages. 109-116 - Thomas Fahringer, Eduard Mehofer:
Problem and Machine Sensitive Communication Optimization. 117-124 - Gerald Roth, Ken Kennedy:
Loop Fusion in High Performance Fortran. 125-132 - Marta Jiménez, José M. Llabería, Agustín Fernández, Enric Morancho:
A General Algorithm for Tiling the Register Level. 133-140
Metacomputing and Cluster0Based Application
- Neil T. Spring, Richard Wolski:
Application Level Scheduling of Gene Sequence Comparison on Metacomputers. 141-148 - Toshiya Kimura, Hiroshi Takemiya:
Local Area Metacomputing for Multidisciplinary Problems: A Case Study for Fluid/Structure Coupled Simulation. 149-156 - Dingchao Li, Yuji Iwahori, Naohiro Ishii:
Exploiting Heterogeneous Parallelism in the Presence of Communication Delays. 157-164 - Jörg Henrichs:
Optimizing and Load Balancing Metacomputing Applications. 165-171 - Cosimo Anglano:
Predicting Parallel Applications Performance on Non-Dedicated Cluster Platforms. 172-179
Compilation Technology
- François Bodin, Yann Mével, Rene Quiniou:
A User Level Program Transformation Tool. 180-187 - William M. Pottenger:
The Role of Associativity and Commutativity in the Detection and Transformation of Loop-level Parallelism. 188-195 - Weng-Long Chang, Chih-Ping Chu:
The Infinity Lambda Test. 196-203 - Sungdo Moon, Mary W. Hall, Brian R. Murphy:
Predicated Array Data-flow Analysis for Run-time Parallelization. 204-211 - Byoungro So, Sungdo Moon, Mary W. Hall:
Measuring the Effectiveness of Automatic Parallelization in SUIF. 212-219
Distributed Software Structures
- Maciej Brodowicz, Olin G. Johnson:
PARADISE: An Advanced Featured Parallel File System. 220-226 - Jan-Jan Wu, Pangfeng Liu:
Distributed Data Structure Design for Scientific Computation. 227-234 - Lars Lundberg, Daniel Häggander:
Bounding on the Gain of Optimizing Data Layout in Vector Processors. 235-242
Software Support for Memory Hierarchy Management
- Francis O'Carroll, Hiroshi Tezuka, Atsushi Hori, Yutaka Ishikawa:
The Design and Implementation of Zero Copy MPI Using Commodity Hardware with a High Performance Network. 243-250 - Cheng Liao, Dongming Jiang, Liviu Iftode, Margaret Martonosi, Douglas W. Clark:
Monitoring Shared Virtual Memory Performance on a Myrinet-based PC Cluster. 251-258 - Takashi Matsumoto, Kei Hiraki:
MBCF: A Protected and Virtualized High-Speed User-Level Memory-Based Communication Facility. 259-266 - Osamu Tatebe, Yuetsu Kodama, Satoshi Sekiguchi, Yoshinori Yamaguchi:
Highly Efficient Implementation of MPI Point-to-Point Communication Using Remote Memory Operations. 267-273 - Angelos Bilas, Liviu Iftode, Jaswinder Pal Singh:
Evaluation of Hardware Write Propagation Support for Next-generation Shared Virtual Memory Clusters. 274-281
Parallel Applications and Algorithms
- Paul D. Coddington, Sung Hoon Ko:
Techniques for Empirical Testing of Parallel Random Number Generators. 282-288 - Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam:
Evaluation of High Performance Multicache Parallel Texture Mapping. 289-296 - Venkatram Krishnaswamy, Prithviraj Banerjee:
Parallel Compiled Event Driven VHDL Simulation. 297-304 - Andrew Sohn, Yuetsu Kodama:
Load Balanced Parallel Radix Sort. 305-312 - Kenji Suehiro, Hitoshi Murai, Yoshiki Seo:
Integer Sorting on Shared-Memory Vector Parallel Computers. 313-320
Keynote
- Kei Hiraki, Junji Tamatsukuri, Takashi Matsumoto:
Speculative Execution Model with Duplication. 321-328
Multithreaded Systems
- Suvas Vajracharya, Dirk Grunwald:
Dependence Driven Execution for Multiprogrammed Multiprocessor. 329-336 - Eleftherios D. Polychronopoulos, Xavier Martorell, Dimitrios S. Nikolopoulos, Jesús Labarta, Theodore S. Papatheodorou, Nacho Navarro:
Kernel-level Scheduling for the Nano-threads Programming Model. 337-344 - Jeong-Si Kim, Yong-Kee Jun:
Scalable On-the-fly Detection of the First Races in Parallel Programs. 345-352 - Gabriel Rivera, Chau-Wen Tseng:
Eliminating Conflict Misses for High Performance Architectures. 353-360
Prefetching
- Matthias M. Müller, Thomas M. Warschko, Walter F. Tichy:
Prefetching on the Cray-T3E. 361-368 - Pablo Ibáñez, Víctor Viñals, José Luis Briz, María Jesús Garzarán:
Characterization and Improvement of Load/Store Cache-based Prefetching. 369-376 - Chi-Hung Chi, Chin-Ming Cheung:
Hardware-driven Prefetching for Pointer Data References. 377-384 - Ricardo Bianchini, Raquel Pinto, Claudio Luis de Amorim:
Data Prefetching for Software DSMs. 385-392
Interconnection Networks
- Yomin Hou, Chien-Min Wang, Lih-Hsing Hsu:
Depth Contention-free Broadcasting on Torus Networks. 393-400 - Enrique V. Carrera, Ricardo Bianchini:
OPTNET: A Cost-effective Optical Network for Multiprocessors. 401-408 - Cruz Izu, Agustin Arruabarrena:
Applying Segment Routing to k-ary n-cube Networks. 409-416 - Sajal K. Das, Daniel J. Harvey, Rupak Biswas:
Dynamic Load Balancing for Adaptive Meshes Using Symmetric Broadcast Networks. 417-424
Keynote
- Roger Espasa, Mateo Valero, James E. Smith:
Vector Architectures: Past, Present and Future. 425-432
Architecture
- Rakefet Kol, Ran Ginosar:
Kin: A High Performance Asynchronous Processor Architecture. 433-440 - David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
Resource Widening Versus Replication: Limits and Performance-cost Trade-off. 441-448 - Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens:
Utilizing Reuse Information in Data Cache Management. 449-456 - Stefanos Kaxiras, Stein Gjessing, James R. Goodman:
A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-memory Multiprocessors. 457-464
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.