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ICCD 2010: Amsterdam, The Netherlands
- 28th International Conference on Computer Design, ICCD 2010, 3-6 October 2010, Amsterdam, The Netherlands, Proceedings. IEEE Computer Society 2010, ISBN 978-1-4244-8936-7
- Peter-Michael Seidel, Georgi Gaydadjiev
, Sofiène Tahar, Lars J. Svensson:
Welcome to ICCD 2010! - Wolfgang J. Paul:
Computational models for the age of multicore processing. - Felix Eberli:
Automotive embedded driver assistance: A real-time low-power FPGA stereo engine using semi-global matching. - David Brash:
Recent additions to the ARMv7-A architecture.
Architecture Innovation for High Performance
- Rafael Ubal, Julio Sahuquillo
Out-of-order retirement of instructions in sequentially consistent multiprocessors. 1-8 - Daniel M. Kopta, Josef B. Spjut, Erik Brunvand, Al Davis:
Efficient MIMD architectures for high-performance ray tracing. 9-16 - Anup Das
A study on performance benefits of core morphing in an asymmetric multicore processor. 17-22
Synchronous Circuits and Interfaces
- Jean-Michel Chabloz, Ahmed Hemani:
Lowering the latency of interfaces for rationally-related frequencies. 23-30 - Rick J. M. Nas, C. H. van Berkel:
High throughput, low set-up time, reconfigurable linear Feedback Shift Registers. 31-37 - Rami A. Abdallah, Naresh R. Shanbhag:
Robust and energy-efficient DSP systems via output probability processing. 38-44
Simulation, Optimization and Scheduling
- Bin Xue, Sandeep K. Shukla
Optimization of back pressure and throughput for latency insensitive systems. 45-51 - Yue Qian, Zhonghai Lu, Qiang Dou:
QoS scheduling for NoCs: Strict Priority Queueing versus Weighted Round Robin. 52-59 - Stefano Frache, Mariagrazia Graziano, Maurizio Zamboni
A flexible simulation methodology and tool for nanoarray-based architectures. 60-67 - Zhuo Ruan, Kurtis Cahill, David A. Penry:
Elaboration-time synthesis of high-level language constructs in SystemC-based microarchitectural simulators. 68-75
High Performance Cache Architecture
- Rami Sheikh, Mazen Kharbutli:
Improving cache performance by combining cost-sensitivity and locality principles in cache replacement algorithms. 76-83 - Ali Shafiee, Narges Shahidi, Amirali Baniasadi:
Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors. 84-91 - Chuanjun Zhang, Bing Xue:
A tag-based cache replacement. 92-97 - Masayuki Sato
A voting-based working set assessment scheme for dynamic cache resizing mechanisms. 98-105 - Samira Manabi Khan, Daniel A. Jiménez:
Insertion policy selection using Decision Tree Analysis. 106-111
Energy/Area efficient Circuit Design in Conventional and Emerging Technologies
- Shi-Ting Zhou, Sumeet Katariya, Hamid Reza Ghasemi, Stark C. Draper
Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC. 112-117 - Morteza Damavandpeyma, Sander Stuijk
Thermal-aware scratchpad memory design and allocation. 118-124 - Shruti Patil, Andrew Lyle, Jonathan D. Harms, David J. Lilja, Jianping Wang:
Spintronic logic gates for spintronic data using magnetic tunnel junctions. 125-131 - Yehua Su, Wenjing Rao:
On mismatch number distribution of nanocrossbar logic mapping. 132-137 - Mehrdad Khatir, Hassan Ghasemzadeh Mohammadi, Alireza Ejlali
Sub-threshold charge recovery circuits. 138-144 - Weiguo Tang, Lei Wang:
Data rate maximization by adaptive thresholding RF power management under renewable energy. 145-150 - Marco Cannizzaro, Weiwei Jiang, Steven M. Nowick:
Practical completion detection for 2-of-N delay-insensitive codes. 151-158
Real-Time and Embedded Systems
- Linwei Niu:
Rate-monotonic scheduling for reducing system-wide energy consumption for hard real-time systems. 159-165 - Xiaorong Zhang, He Huang
Design and implementation of a special purpose embedded system for neural machine interface. 166-172 - Ali Sharif Ahmadian, Mahdieh Hosseingholi, Alireza Ejlali
A control-theoretic energy management for fault-tolerant hard real-time systems. 173-178 - Matthias Müller, Joachim Gerlach, Wolfgang Rosenstiel:
RTOS-aware modeling of embedded hardware/software systems. 179-186 - Paolo Burgio
Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems. 187-194
Advances in Physical Design and Synthesis
- Glauco Borges Valim dos Santos, Tiago Reimann, Marcelo O. Johann, Ricardo Reis
The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms. 195-202 - Zhi-Wei Chen, Jin-Tai Yan:
Routability-driven flip-flop merging process for clock power reduction. 203-208 - Vinayak Honkote, Baris Taskin:
Skew-aware capacitive load balancing for low-power zero clock skew rotary oscillatory array. 209-214 - John Lee, Puneet Gupta
Incremental gate sizing for late process changes. 215-221 - Sanghamitra Roy
Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization. 222-228 - Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis:
Boolean factoring with multi-objective goals. 229-234
Circuits for Arithmetic, Cryptography and Signal Processing
- Patricio Bulic, Zdenka Babic, Aleksej Avramovic:
A simple pipelined logarithmic multiplier. 235-240 - Malte Baesler, Sven-Ole Voigt, Thomas Teufel:
A radix-10 digit recurrence division unit with a constant digit selection function. 241-246 - Somayeh Timarchi, Mahmood Fazlali
A unified addition structure for moduli set {2n-1, 2n, 2n+1} based on a novel RNS representation. 247-252 - Shohreh Sharif Mansouri, Elena Dubrova:
Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms. 253-259 - Vaibhav Gupta, Georgios Karakonstantis, Debabrata Mohapatra, Kaushik Roy:
VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture. 260-265 - Jason Thong, Nicola Nicolici:
Combined optimal and heuristic approaches for multiple constant multiplication. 266-273
Multiprocessor Systems
- Zvika Guz, Oved Itzhak, Idit Keidar, Avinoam Kolodny, Avi Mendelson, Uri C. Weiser:
Threads vs. caches: Modeling the behavior of parallel workloads. 274-281 - Peter Poplavko, Marc Geilen
Predicting the throughput of multiprocessor applications under dynamic workload. 282-288 - Pengfei Gou, Qingbo Li, Yinghan Jin, Qi Zheng, Bing Yang, Mingyan Yu, Jinxiang Wang:
M5 based EDGE architecture modeling. 289-296 - Michael A. Baker, Karam S. Chatha:
A lightweight run-time scheduler for multitasking multicore stream applications. 297-304 - Peter van Stralen, Andy D. Pimentel
Scenario-based design space exploration of MPSoCs. 305-312
Best Papers Session
- Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham:
Toward reliable SRAM-based device identification. 313-320 - Wei Shi, Zhiying Wang, Hongguang Ren, Ting Cao, Wei Chen, Bo Su, Hongyi Lu:
DSS: Applying asynchronous techniques to architectures exploiting ILP at compile time. 321-327 - Navid Toosizadeh, Safwat G. Zaky, Jianwen Zhu:
Using variable clocking to reduce leakage in synchronous circuits. 328-335 - Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang
Efficient provably good OPC modeling and its applications to interconnect optimization. 336-341 - Seokin Hong, Soontae Kim
Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU. 342-349
Architecture Innovation for System Robustness and Performance
- Arun K. Kanuparthi, Mohamed Zahran
Feasibility study of dynamic Trusted Platform Module. 350-355 - Nicolas Zea, John Sartori, Ben Ahrens, Rakesh Kumar:
Optimal power/performance pipelining for error resilient processors. 356-363 - Hans Vandierendonck
Implicit hints: Embedding hint bits in programs without ISA changes. 364-369 - Dongkyun Ahn, Gyungho Lee:
Countering code injection attacks with TLB and I/O monitoring. 370-375
Modeling and Optimization for Test Development
- Andreas Merentitis, Antonis M. Paschalis
Energy optimal on-line Self-Test of microprocessors in WSN nodes. 376-383 - Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron
Temperature-to-power mapping. 384-389 - Baris Arslan, Alex Orailoglu:
Delay test quality maximization through process-aware selection of test set size. 390-395 - Ahmad Patooghy
Crosstalk modeling to predict channel delay in Network-on-Chips. 396-401 - Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita:
Generation of I/O sequences for a high-level design from those in post-silicon for efficient post-silicon debugging. 402-408
Energy and Performance Optimization
- Jeff Pool, Anselmo Lastra, Montek Singh:
An energy model for graphics processing units. 409-416 - Benedikt Dietrich, Swaroop Nunna, Dip Goswami, Samarjit Chakraborty
LMS-based low-complexity game workload prediction for DVFS. 417-424 - Samuel Antao, Leonel Sousa
Exploiting SIMD extensions for linear image processing with OpenCL. 425-430 - Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden:
A co-processor approach for accelerating data-structure intensive algorithms. 431-438
Networks-on-Chip
- Tushar Krishna, Jacob Postman, Christopher Edmonds, Li-Shiuan Peh, Patrick Chiang:
SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS. 439-446 - Arseniy Vitkovskiy, Vassos Soteriou
A fine-grained link-level fault-tolerant mechanism for networks-on-chip. 447-454 - JunBok You, Daniel Gebhardt, Kenneth S. Stevens:
Bandwidth optimization in asynchronous NoCs by customizing link wire length. 455-461 - Shubo Qi, Minxuan Zhang, Jinwen Li, Tianlei Zhao, Chengyi Zhang, Shaoqing Li:
A high performance router with dynamic buffer allocation for on-chip interconnect networks. 462-467
Verification and Design for Test with Reduced Overhead
- Luigi Di Guglielmo, Franco Fummi, Nicola Orlandi, Graziano Pravadelli
DDPSL: An easy way of defining properties. 468-473 - Jia Li, Dong Xiang:
DfT optimization for pre-bond testing of 3D-SICs containing TSVs. 474-479 - Thomas Indlekofer, Michael Schnittger, Sybille Hellebrand:
Efficient test response compaction for robust BIST using parity sequences. 480-485 - Debapriya Chatterjee, Valeria Bertacco:
EQUIPE: Parallel equivalence checking with GP-GPUs. 486-493
Energy Efficient Architecture
- Christos Strydis
Identifying optimal generic processors for biomedical implants. 494-501 - Hyung Beom Jang, Jinhang Choi, Ikroh Yoon, Sung-Soo Lim, Seungwon Shin
Exploiting application-dependent ambient temperature for accurate architectural simulation. 502-508 - Subhra Mazumdar, Dean M. Tullsen
Inter-socket victim cacheing for platform power reduction. 509-514 - Meltem Ozsoy, Yusuf Onur Koçberber, Mehmet Kayaalp, Oguz Ergin
Dynamic register file partitioning in superscalar microprocessors for energy efficiency. 515-520
Power and Thermal Analysis and Optimization
- Shervin Sharifi, Tajana Simunic Rosing:
Package-Aware Scheduling of embedded workloads for temperature and Energy management on heterogeneous MPSoCs. 521-527 - Yu Liu, Kaijie Wu:
Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability. 528-533 - Michel Rogers-Vallée, Marc-André Cantin, Laurent Moss, Guy Bois:
IP characterization methodology for fast and accurate power consumption estimation at transactional level model. 534-541 - Junjun Gu, Gang Qu, Lin Yuan:
Enhancing dual-Vt design with consideration of on-chip temperature variation. 542-547 - Quang Dinh, Deming Chen, Martin D. F. Wong
BDD-based circuit restructuring for reducing dynamic power. 548-554
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