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ICCAD 2001: San Jose, California, USA
- Rolf Ernst:
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2001, San Jose, CA, USA, November 4-8, 2001. IEEE Computer Society 2001, ISBN 0-7803-7249-2
Dynamic Verification
- Murali Kudlugi, Charles Selvidge, Russell Tessier:
Static Scheduling of Multi-Domain Memories For Functional Verification. 2-9 - Scott A. Taylor, Carl Ramey, Craig Barner, David Asher:
A Simulation-Based Method for the Verification of Shared Memory in Multiprocessor Systems. 10-17 - Jinsheng Xu, Moon-Jung Chung:
Predicting the Performance of Synchronous Discrete Event Simulation Systems. 18-
System-Level Exploration and Design
- Tony Givargis, Frank Vahid, Jörg Henkel:
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip. 25-30 - Paul Lieverse, Todor P. Stefanov, Pieter van der Wolf, Ed F. Deprettere:
System Level Design with Spade: an M-JPEG Case Study. 31-38 - Gokhan Memik, William H. Mangione-Smith, Wendong Hu:
NetBench: A Benchmarking Suite for Network Processors. 39-
Interconnect Planning
- Amir H. Ajami, Kaustav Banerjee, Massoud Pedram:
Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion. 44-48 - Xiaoping Tang, Ruiqi Tian, Hua Xiang, D. F. Wong
:
A New Algorithm for Routing Tree Construction with Buffer Insertion and Wire Sizing under Obstacle Constraints. 49-56 - Bret M. Victor, Kurt Keutzer:
Bus Encoding to Prevent Crosstalk Delay. 57-
Analog Macromodeling
- Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling:
Behavioral Modeling of Analog Circuits by Wavelet Collocation Method. 65-69 - Walter Daems, Georges G. E. Gielen
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing. 70-74 - Yu-Min Lee, Charlie Chung-Ping Chen:
Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method. 75-
Embedded Tutorial: Platform-Based Designs
Embedded Tutorial: VLSI Microsystems: The Power of Many
Sequential Synthesis
- Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton:
Sequential SPFDs. 84-90 - Enrique San Millán, Luis Entrena, José Alberto Espejo:
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. 91-94 - Ingmar Neumann, Wolfgang Kunz:
Placement Driven Retiming with a Coupled Edge Timing Model. 95-102 - Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko
Solution of Parallel Language Equations for Logic Synthesis. 103-
Compiler Techniques in System Level Design
- Cagdas Akturan, Margarida F. Jacome:
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors. 112-118 - Prabhat Jain, Srinivas Devadas, Daniel W. Engels, Larry Rudolph:
Software-Assisted Cache Replacement Mechanisms for Embedded Systems. 119-126 - Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzadeh, Majid Sarrafzadeh:
Instruction Generation for Hybrid Reconfigurable Systems. 127-
Routing Architecture and Techniques for FPGAs
- Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska:
Interconnect Resource-Aware Placement for Hierarchical FPGAs. 132-136 - Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung:
A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. 137-143 - Vinay Verma, Shantanu Dutt:
A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs. 144-
Interconnect Performance and Reliability Optimization
- Xiaohai Wu, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu, Wayne Wei-Ming Dai:
Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques. 153-157 - Kaustav Banerjee, Amit Mehrotra:
Coupled Analysis of Electromigration Reliability and Performance in ULSI Signal Nets. 158-164 - TingYen Chiang, Kaustav Banerjee, Krishna Saraswat:
Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. 165-
Panel
- Andreas Kuehlmann, Robert W. Dutton, Paul D. Franzon, Seth Copen Goldstein, Philip Luekes, Eric Parker, Thomas N. Theis:
Will Nanotechnology Change the Way We Design and Verify Systems? (Panel). 174
Circuit Structure in Fromal Verification
- Jason Baumgartner, Andreas Kuehlmann:
Min-Area Retiming on Dynamic Circuit Structures. 176-182 - Dominik Stoffel, Wolfgang Kunz:
Verification of Integer Multipliers on the Arithmetic Bit Level. 183-189 - Ying-Tsai Chang, Kwang-Ting Cheng
Induction-Based Gate-Level Verification of Multipliers. 190-
System Level Power and Performance Modeling
- Giovanni Beltrame, Carlo Brandolese, William Fornaciari
An Assembly-Level Execution-Time Model for Pipelined Architectures. 195-200 - Mahmut T. Kandemir, Ugur Sezer, Victor Delaluz:
Improving Memory Energy Using Access Pattern Classification. 201-206 - Radu Marculescu
System-Level Power/Performance Analysis of Portable Multimedia Systems Communicating over Wireless Channels. 207-
Topics in Physical Synthesis
- Thomas Kutzschebauch, Leon Stok:
Congestion Aware Layout Driven Logic Synthesis. 216-223 - Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli:
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. 224-231 - Hua Xiang, Xiaoping Tang, D. F. Wong
An Algorithm for Simultaneous Pin Assignment and Routing. 232-
Model Order Reduction
- Luca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob K. White:
Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed Interconnect. 240-244 - Carlos P. Coelho, Joel R. Phillips, Luís Miguel Silveira
A Convex Programming Approach to Positive Real Rational Approximation. 245-251 - Michal Rewienski, Jacob White:
A Trajectory Piecewise-Linear Approach to Model Order Reduction and Fast Simulation of Nonlinear Circuits and Micromachined Devices. 252-
Embedded Tutorial: Embedded Software and Systems
- Niraj K. Jha:
Low Power System Scheduling and Synthesis. 259-263 - Lothar Thiele:
Integral Design Representations for Embedded Systems. 264 - Diederik Verkest, Peng Yang, Chun Wong, Paul Marchal:
Optimisation Problems for Dynamic Concurrent Task-Based Systems. 265-
Embedded Tutorial
- Domine Leenaerts, Rob A. Rutenbar
Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design.
BDDs and SAT
- Lintao Zhang, Conor F. Madigan, Matthew W. Moskewicz, Sharad Malik
Efficient Conflict Driven Learning in Boolean Satisfiability Solver. 279-285 - Aarti Gupta
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. 286-292 - Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang:
Non-linear Quantification Scheduling in Image Computation. 293-
Convergence of Abstractions in High-Level Synthesis
- Armita Peymandoust, Giovanni De Micheli:
Symbolic Algebra and Timing Driven Data-flow Synthesis. 300-305 - Diana Marculescu, Anoop Iyer:
Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis. 306-313 - Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
A System for Synthesizing Optimized FPGA Hardware from MATLAB. 314-319 - Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi:
Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. 320-
Signal Integrity and Clock Design
- James D. Z. Ma, Lei He:
Formulae and Applications of Interconnect Estimation Considering Shield Insertion and Net Ordering. 327-332 - Haihua Su, Sachin S. Sapatnekar:
Hybrid Structured Clock Network Construction. 333-336 - Yonghee Im, Kaushik Roy:
CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic. 337-
Analog Synthesis
- Helmut E. Graeb, Stephan Zizala, Josef Eckmüller, Kurt Antreich:
The Sizing Rules Method for Analog Integrated Circuit Design. 343-349 - Michael Krasnicki, Rodney Phelps, James R. Hellums, Mark McClung, Rob A. Rutenbar
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits. 350-357 - Peter J. Vancorenland, Geert Van der Plas
A Layout-Aware Synthesis Methodology for RF Circuits. 358-
Manufacturing Test: Stuck-at to Crosstalk
- Seiji Kajihara, Kohei Miyase:
On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits. 364-369 - Chen Wang, Irith Pomeranz, Sudhakar M. Reddy:
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. 370-374 - Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota:
Crosstalk Fault Detection by Dynamic Idd. 375-
Architecture Oriented Scheduling
- Jianwen Zhu, Edward S. Rogers Sr.:
Color Permutation: An Iterative Algorithm for Memory Packing. 380-383 - Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess:
Constraint Satisfaction for Relative Location Assignment and Scheduling. 384-390 - Seda Ogrenci Memik, Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh:
A Super-Scheduler for Embedded Reconfigurable Systems. 391-
New Techniques in Routing
- Jason Cong, Jie Fang, Yan Zhang VI:
Multilevel Approach to Full-Chip Gridless Routing. 396-403 - Fan Mo, Abdallah Tabbara, Robert K. Brayton:
A Force-Directed Maze Router. 404-407 - Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. 408-
Issues in Substrate Coupling
- Joe Kanapka, Jacob K. White:
Highly Accurate Fast Methods for Extraction and Sparsification of Substrate Coupling Based on Low-Rank Approximation. 417-423 - Minqing Liu, Tiejun Yu, Wayne Wei-Ming Dai:
Fast 3-D Inductance Extraction in Lossy Multi-Layer Substrate. 424-429 - Joel R. Phillips, Luís Miguel Silveira
Simulation Approaches for Strongly Coupled Interconnect Systems. 430-
Combinational Optimization
- Jan Hlavicka, Petr Fiser
BOOM - A Heuristic Boolean Minimizer. 439-442 - Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Faster SAT and Smaller BDDs via Common Function Structure. 443-448 - Rupesh S. Shelar, Sachin S. Sapatnekar:
Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. 449-452 - Jennifer L. Wong
A Probabilistic Constructive Approach to Optimization Problems. 453-
Real Time Scheduling and Performance Analysis
- Amit Sinha, Anantha P. Chandrakasan:
Energy Efficient Real-Time Scheduling. 458-470 - Hongchao (Stephanie) Liu, Xiaobo Sharon Hu
Efficient Performance Estimation for General Real-Time Task Systems. 464-470 - Felice Balarin:
Stars in VCC: Complementing Simulation with Worst-Case Analysis. 471-
Power Analysis
- Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm:
Multigrid-Like Technique for Power Grid Analysis. 480-487 - Daler N. Rakhmatov, Sarma B. K. Vrudhula:
An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. 488-493 - José Luis Rosselló, Jaume Segura:
Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. 494-
Timing and Noise Analysis
- Clayton B. McDonald, Randal E. Bryant:
A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells. 501-506 - Jin-Fuw Lee, Daniel L. Ostapko, Jeffery Soreff, C. K. Wong:
On the Signal Bounding Problem in Timing Analysis. 507-514 - Alexey Glebov, Sergey Gavrilov
False-Noise Analysis using Logic Implications. 515-
System Level Test and Reliability
- Erik Larsson
The Design and Optimization of SOC Test Solutions. 523-530 - Donald B. Shaw, Dhamin Al-Khalili, Côme Rozon:
Accurate CMOS Bridge Fault Modeling with Neural Network-Based VHDL Saboteurs. 531-536 - Kaijie Wu, Ramesh Karri
Algorithm Level Re-Computing - A Register Transfer Level Concurrent Error Detection Technique. 537-
Power Issues in High Level Synthesis
- Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan
Transient Power Management Through High Level Synthesis. 545-552 - Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu:
An Integrated Data Path Optimization for Low Power Based on Network Flow Method. 553-559 - Gang Qu:
What is the Limit of Energy Saving by Dynamic Voltage Scaling? 560-
Advances in Placement
- Oluf Faroe, David Pisinger
Local Search for Final Placement in VLSI Design. 565-572 - Xiaojian Yang, Ryan Kastner, Majid Sarrafzadeh:
Congestion Reduction During Placement Based on Integer Programming. 573-576 - Prakash Gopalakrishnan, Rob A. Rutenbar:
Direct Transistor-Level Layout for Digital Blocks. 577-
Interconnect Analysis and Extraction
- Payam Heydari, Massoud Pedram:
Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation. 586-591 - Zhenhai Zhu, Jingfang Huang, Ben Song, Jacob K. White:
Improving the Robustness of a Surface Integral Formulation for Wideband Impendance Extraction of 3D Structures. 592-597 - Steven C. Chan, Kenneth L. Shepard:
Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits. 598-
Don't Care Optimization and Boolean Matching
- Chih-Wei Jim Chang, Malgorzata Marek-Sadowska:
Single-Pass Redundancy Addition and Removal. 606-609 - Jovanka Ciric, Carl Sechen:
Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. 610-617 - Robert K. Brayton:
Compatible Observability Don't Cares Revisited. 618-
Power Saving Techniques for Embedded Processors
- Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr:
A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. 625-630 - Subash Chandar G., Mahesh Mehendale, R. Govindarajan:
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. 631-634 - Sri Parameswaran
I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. 635-
Embedded Tutorial: IC Power Distribution Challenges
- Sudhakar Bobba, Tyler Thorp, Kathirgamar Aingaran, Dean Liu:
IC Power Distribution Challenges. 643-650 - Shen Lin, Norman Chang:
Challenges in Power-Ground Integrity. 651-
Panel
- Rob A. Rutenbar, Olivier Coudert, Patrick Groeneveld, Jürgen Koehl, Scott Peterson, Vivek Raghavan, Naresh Soni:
Automatic Hierarchical Design: Fantasy or Reality? (Panel). 656
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