default search action
EWDTS 2010: St. Petersburg, Russia
- 2010 East-West Design & Test Symposium, EWDTS 2010, St. Petersburg, Russia, September 17-20, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-9555-9
- Maksim Jenihhin
, Jaan Raik
An approach for PSL assertion coverage analysis with high-level decision diagrams. 13-16 - Daniele Rossi
Secure communication protocol for wireless sensor networks. 17-20 - Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Hardware reduction for FSM - Based control units using PAL technology. 21-24 - Liudmila D. Cheremisinova, Dmitry Ya. Novikov:
SAT-based group method for verification of logical descriptions with functional indeterminacy. 25-28 - Vazgen Melikyan, Davit Mirzoyan, Gor Petrosyan:
A process variation detection method. 30-33 - Sargis Abovyan, Gor Petrosyan, Tigran Harutyunyan:
Architecture of queued-free crossbar for on-chip networks. 34-36 - Gor Petrosyan, Sargis Abovyan, Tigran Harutyunyan:
Modeling on-chip variations in digital circuits using statistical timing analysis. 37-39 - Vazgen Melikyan, S. Karapetyan, Davit Mirzoyan, Eduard Babayan:
Stable current and voltage generation under process variation. 40-42 - Janusz Sosnowski
Self-testing of microcontrollers in the field. 43-46 - Stefano Di Carlo
Exploring modeling and testing of NAND flash memories. 47-50 - Vladimir Hahanov
Coverage method for FPGA fault logic blocks by spares. 51-56 - Palanichamy Manikandan
Experiments with ABIST test methodology applied to path delay fault testing. 59-63 - Nikolaos Mavrogiannakis, Costas Argyrides, Dhiraj K. Pradhan:
Improving reliability for bit parallel finite field multipliers using Decimal Hamming. 69-72 - Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski:
Microprogram control unit with code sharing and extended microinstruction format. 73-76 - Vladimir Hahanov
Testing and verification of HDL-models for SoC components. 77-82 - Branka Medved Rogina, Peter Skoda, Karolj Skala, Ivan Michieli, Maja Vlah, Sinisa Marijan:
Metastability testing at FPGA circuit design using propagation time characterization. 80-85 - Osnat Keren, Ilya Levin
Fault tolerance of decomposed PLAs. 86-91 - A. Andrashov, Vyacheslav S. Kharchenko
Verification of FPGA electronic designs for nuclear reactor trip systems: test- and invariant-based methods. 92-97 - Vladimir Hahanov
Cyber space and brain-like computing. 98-109 - Vladimir Hahanov
Vector logic analysis of associative matrices. 110-117 - Vladimir Hahanov
Table data structures for cyber space. 118-122 - Vladimir Hahanov
Process models for analyzing associative data structures. 123-127 - Mark M. Gourary, Sergey G. Rusakov
A technique to accelerate the Vector Fitting algorithm for interconnect simulation. 127-130 - Mark M. Gourary, Sergey G. Rusakov
Frequency domain techniques for simulation of oscillators. 131-134 - Alexander V. Drozd, Vyacheslav S. Kharchenko
Component-based safety-oriented on-line testing of digital systems. 135-140 - F. Podyablonsky, N. Kascheev:
Generalized faulty block model for automatic test pattern generation. 141-143 - Natalia V. Chebykina, Sergey G. Mosin
A technique of optimal built-in self-test circuitries generation. 145-148 - Victor I. Djigan
Applied library of adaptive lattice filters for nonstationary signal processing. 149-152 - Andrey Zakonov, Oleg A. Stepanov, Anatoly Shalyto
GA-based and design by contract approach to test generation for EFSMs. 152-155 - Vladislav A. Lesnikov
Implementation of a new paradigm in design of IIR digital filters. 156-159 - Anjela Yu. Matrosova, Ekaterina Nikolaeva:
PDFs testing of combinational circuits based on covering ROBDDs. 160-163 - Anzhela Yu. Matrosova, Valeriy B. Lipsky, Alexey Melnikov, Virendra Singh:
Path delay faults and ENF. 164-167 - Valentina Andreeva
Test minimization technique for multiple stuck-at faults of combinational circuit. 168-170 - Sergey Ostanin, R. Muchamedov:
Testable combinational circuit design based on ZDD-implementation of ISOP Boolean function. 171-174 - Gamlet S. Khanyan:
Level quantization effect on accuracy of fast Fourier transform algorithm. 175-178 - S. O. Churayev, B. T. Matkarimov, T. T. Paltashev:
On-chip measurements of standard-cell propagation delay. 179-181 - S. O. Churayev, B. T. Matkarimov:
FPGA FFT implementation. 183-185 - Volodymyr Obrizan:
A method for automatic generation of an RTL-interface from a C++ description. 186-189 - Aleksandr V. Shishkin
OFDM-based audio watermarking for electronic radiotelephone identification. 190-194 - George Dan Mois
Reconfiguration and hardware agents in testing and repair of distributed systems. 195-198 - Aditi Kajala
On selection of state variables for delay test of identical functional units. 200-203 - Vladimir Hahanov
Metrics of vector logic algebra for cyber space. 204-207 - Vladimir Hahanov
Cyber space evolution. 208-214 - Vladimir Hahanov
Logical method for detecting faults by fault detection table. 215-217 - Stefano Di Carlo
EDACs and test integration strategies for NAND flash memories. 218-221 - Nadereh Hatami, Marco Indaco, Paolo Prinetto, Gabriele Tiotto:
Communication interface synthesis from TLM 2.0 to RTL. 222-226 - Nadereh Hatami, Paolo Prinetto, Gabriele Tiotto:
Sign Language synthesis using hand motion acquisition. 226-229 - Victor V. Panteleev:
An algorithm of timing recovery for modem with M-ary alphabets APK-signals. 230-235 - Victor V. Panteleev, Alexander I. Vakaruk:
Engineering-maintenance methods of the calculation xDSL-lines. 236-241 - Sergei G. Krutchinsky, Michael S. Tsibin, Alexey E. Titov:
Common-mode signal minimization in differential stage. 242-245 - Sergei G. Krutchinsky:
Optimization of sensitivity dominating parameters OA in selective IP blocks. 246-249 - Irina D. Pletneva, Victor I. Djigan
Adaptive array based on "Multicore" DSP family and Linearly Constrained constant modulus IQRD RLS algorithm. 254-257 - Victor I. Djigan
Performance investigation of antenna arrays by means of virtual instruments. 258-261 - Gamlet S. Khanyan:
Level quantization effects in digital signal processing by discrete Fourier transform method. 262-265 - Igor Ilyin, Rostislav Grushvitsky:
Internal structure of software application for controlling devices via JTAG 1149 interface. 264-266 - Vladimir Volkov
Straight edge extraction and localization on noisy images. 267-270 - G. V. Kulikov, A. U. Unger, P. G. Suhanov:
A digital implementation of multi-h CPM modem. 271-273 - Stanislav S. Gritsutenko
Quantization step dispersion of direct transformation ADC. 274-277 - Alexander B. Sergienko
Blind carrier frequency offset estimation for QAM signals based on weighted 4th power of signal samples. 278-281 - Vladislav A. Lesnikov
A new paradigm in design of IIR digital filters. 282-285 - Yuriy A. Skobtsov
Evolutionary approach to test generation of sequential digital circuits with multiple observation time strategy. 286-291 - Helen V. Kharchenko
Two-criterial DSSS synchronization method efficiency research. 289-299 - Dmitriy V. Speranskiy:
An entropic approach to diagnostic information compression. 292-299 - Alexander Zemliak, M. Torres, Fernando Reyes-Cortés, Sergio Vergara, Tatiana M. Markina:
Dynamic characteristics of different system design strategies. 300-303 - Yegor I. Vdovychenko:
FPGA-based digital phase difference meter. 309 - H. Avetisyan, Gurgen Harutyunyan, Valery A. Vardanian, Yervant Zorian:
An efficient March test for detection of all two-operation dynamic faults from subclass Sav. 310-313 - E. M. Grinkrug, A. R. Shakurov:
Component architecture with runtime type definition. 315-318 - H. H. Asadov, Y. N. Aliyeva, L. A. Bayramova, K. Kh. Ismailov:
New method of multi-level optimization. 319-321 - H. H. Asadov, N. A. Abdullayev, M. J. Kerimov, E. F. Dadashov:
Utilization of variation optimization for location of emitter of random noise signal. 322-323 - H. H. Asadov, N. A. Abdullayev, E. A. Ibrahimov, V. M. Garayev, E. Abbaszadeh:
Information optimization of distributed net of receivers of acoustic noise type signals. 324-325 - H. H. Asadov, N. A. Abdullayev, I. K. Agayev, N. A. Nabiyev, R. T. Rajabli:
Optimization of information - Measuring systems of non-stationary operational regime in multiple measurements mode. 326-327 - H. H. Asadov, N. A. Abdullayev, S. B. Jalilov, N. A. Nabiyev, N. H. Javadov:
On possibility of stabilizing results for multicriteria optimizing linear combination of concurrent functionals. 328-329 - Viney Kumar, Rahul Raj Choudhary, Virendra Singh:
FREP: A soft error resilient pipelined RISC architecture. 330-333 - Anton Tsertov
Testing beyond the SoCs in a lego style. 334-338 - Vitalij D. Pavlenko, Viktor Burdeinyi:
Cluster computing framework based on transparent parallelizing technology. 339-342 - N. S. Vinay, Indira Rawat, Erik Larsson, Manoj Singh Gaur, Virendra Singh:
Thermal aware test scheduling for stacked multi-chip-modules. 343-349 - K. R. Vinutha, Virendra Singh, Anzhela Yu. Matrosova, Manoj Singh Gaur:
Fault grading using Instruction-Execution graph. 350-357 - Dmitry Bagayev, Evsyakov Artem:
System remote control of the robotized complex - Pegas. 358-361 - A. A. Bykau, I. I. Piletsky:
Internet applications testing automation through probabilistic-network programming. 362-365 - Mudar Almadi, Diaa Moamar, Vladimir Ryabtsev:
Methodology of algorithms synthesis of storage devices test diagnosing. 366-370 - Nina Khairova
Building of the logic network of the information area of the corporation. 371-373 - Eduard Atkin
Development of the data-driven readout ASIC for microstrip detectors. 374-375 - Ilia Polian, John P. Hayes:
Advanced modeling of faults in Reversible circuits. 376-381 - Nina Khairova
Use of predicate categories for modelling of operation of the semantic analyzer of the linguistic processor. 382-385 - Alexander V. Drozd, Svetlana Antoshchuk
Increase in reliability of on-line testing methods using natural time redundancy. 386-391 - Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski:
Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. 390-394 - Fatemeh Javaheri, Zainalabedin Navabi:
ESL design methodology for architecture exploration. 395-401 - Amirali Ghofrani, Sheis Abolma'ali, Zahra Najafi Haghi, Zainalabedin Navabi:
A TLM2.0 assertion library with centralized monitoring approach. 402-406 - Vazgen Melikyan, Aristakes Hovsepyan, Tigran Harutyunyan:
Schematic protection method from influence of total ionization dose effects on threshold voltage of MOS transistors. 407-409 - Arezoo Kamran
Virtual tester development using HDL/PLI. 412-415 - Arezoo Kamran
Merit based directed random test generation (MDRTG) scheme for combinational circuits. 416-419 - Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi:
Near optimal machine learning based random test generation. 420-424 - Alexander Adamov
Security risks in hardware: Implementation and detection problem. 425-427 - Homa Alemzadeh
Facilitating testability of TLM FIFO: SystemC implementations. 428-431 - Homa Alemzadeh
Code optimization for enhancing SystemC simulation time. 431-434 - Vazgen Melikyan, Karen Sahakyan, Armen Nazaryan:
5V tolerant power clamps for mixed-voltage IC's in 65nm 2.5V salicided CMOS technology. 434-437 - Dmitri Boulytchev
Hardware description language based on message passing and implicit pipelining. 438-441 - Mikhail Talalay, Konstantin Trushin, Oleg Venger:
Between standard cells and transistors: Layout templates for Regular Fabrics. 442-448 - Alexander Adamov
The problem of Trojan inclusions in software and hardware. 449-451 - Vitaliy Kulanov
Parameterized IP Infrastructures for fault-tolerant FPGA-based systems: Development, assessment, case-study. 452-455 - Mohammad Hashem Haghbayan, Alireza Yazdanpanah, Sara Karamati, Ramyar Saeedi, Zainalabedin Navabi:
Generating test patterns for sequential circuits using random patterns by PLI functions. 456-461 - Mohammad Hossein Sargolzaei
Low cost error tolerant motion estimation for H.264/AVC standard. 461-465 - A. S. Epifanov:
Method of diagnosing FPGA with use of geometrical images. 465-468 - Vladimir Hahanov
System in Package. Diagnosis and embedded repair. 468-472 - Vladimir Hahanov
Technology for faulty blocks coverage by spares. 473-478 - A. V. Babich, Murad Ali Abbas:
The Unicast Feedback models for real-time control protocol. 479-481 - Vladimir Hahanov
Algebra-logical repair method for FPGA logic blocks. 482-487 - Mikhail M. Chupilko:
Constructing test sequences for hardware designs with parallel starting operations using implicit FSM models. 487-490 - Somayyeh Jafarali Jassbi, Mehdi Hosseinzadeh, Keivan Navi:
Redundant Multi-Level one-hot Residue Number System based error correction codes. 491-494 - Sergey Mikhtonyuk, Maksim Davydov, Roman Hwang, Dmitry Shcherbin:
IEEE 1500 compliant test wrapper generation tool for VHDL models. 495-499 - Dmitry Melnik, Olga Lukashenko, Sergey A. Zaychenko
Early detection of potentially non-synchronized CDC paths using structural analysis technique. 500-503 - M. H. Haghbayan, Zainalabedin Navabi:
Architecture design and technical methodology for bus testing. 504-509 - Amirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi:
Assertion based verification in TLM. 509-513 - Alexander Sudnitson, Dmitri Mihhailov, Margus Kruus
Advanced topics of FSM design using FPGA educational boards and web-based tools. 514-517 - Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi:
A mixed HDL/PLI test package. 518-523 - Muhammad Mehdi Lotfinejad, Mohammad Mosleh, Hamid Noori
A novel high speed residue to binary converter design based on the three-moduli set {2n, 2n+1+1, 2n+1-1}. 524-526 - V. A. Tverdokhlebov:
Phase pictures of properties of complex objects of technical diagnostics. 527-530 - Mikhail F. Karavay, Victor S. Podlazov:
Extended complete switch as ideal system network. 530-534 - Yevgeniya Sulema
Image compression: Comparative analysis of basic algorithms. 534-537 - Anatoly I. Petrenko:
Networked VLSI and MEMS designer for Grid. 538-544 - Jiri Jenícek, Ondrej Novák:
COMPAS - Advanced test compressor. 543-548
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-04 20:02 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: