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"Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance."

Yuvraj Singh Dhillon et al. (2006)

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DOI: 10.1109/TVLSI.2006.876104

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/DhillonDCS06
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh:
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 514-524 (2006)

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