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"Clock Data Compensation Aware Digital Circuits Design for Voltage Margin ..."

Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay (2017)

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DOI: 10.1109/TCSI.2017.2695478

access: closed

type: Journal Article

metadata version: 2020-05-22

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  - https://dblp.org/rec/journals/tcas/NaKM17
Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay:
Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2401-2413 (2017)

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