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"An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters."

Masataka Matsui et al. (1989)

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DOI: 10.1109/JSSC.1989.572585

access: closed

type: Journal Article

metadata version: 2024-11-12

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  - https://dblp.org/rec/journals/jssc/MatsuiMUMSUSMO89
Masataka Matsui, Hiroshi Momose, Yukihiro Urakawa, Takeo Maeda, Azuma Suzuki, Nobuaki Urakawa, Katsuhiko Sato, Jun'ichi Matsunaga, Kiyofumi Ochii:
An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters. IEEE J. Solid State Circuits 24(5): 1226-1232 (1989)

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