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"A fast model for analysis and improvement of gate-level circuit reliability."

Chunhong Chen, Ran Xiao (2015)

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DOI: 10.1016/J.VLSI.2015.02.005

access: closed

type: Journal Article

metadata version: 2020-02-20

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Chunhong Chen, Ran Xiao:
A fast model for analysis and improvement of gate-level circuit reliability. Integr. 50: 107-115 (2015)

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