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"A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated ..."

Dipankar Saha et al. (2013)

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DOI: —

access: open

type: Informal or Other Publication

metadata version: 2018-08-13

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  - electronic edition @ arxiv.org (open access)
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  dblp key:
  - journals/corr/SahaBMS13
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  persistent URL:
  - https://dblp.org/rec/journals/corr/SahaBMS13
Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Chandan Kumar Sarkar:
A Low-Voltage, Low-Power 4-bit BCD Adder, designed using the Clock Gated Power Gating, and the DVT Scheme. CoRR abs/1309.7163 (2013)

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