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"A Systolic Architecture of VLSI Implementation of Dynamic Time Warping for ..."

Hong Jeong, Yong Kim (2003)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2006-05-22

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  - electronic edition @ actapress.com
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  dblp key:
  - conf/sip/JeongK03
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  persistent URL:
  - https://dblp.org/rec/conf/sip/JeongK03
Hong Jeong, Yong Kim:
A Systolic Architecture of VLSI Implementation of Dynamic Time Warping for Speech Recognition. SIP 2003: 109-114

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