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"Stage-by-Stage Power Gating Circuit for Ultra-Low-Power Self-Timed Pipeline."

Shuji Sannomiya et al. (2010)

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DOI: —

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type: Conference or Workshop Paper

metadata version: 2010-12-07

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  dblp key:
  - conf/pdpta/SannomiyaMIN10
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  persistent URL:
  - https://dblp.org/rec/conf/pdpta/SannomiyaMIN10
Shuji Sannomiya, Kei Miyagi, Makoto Iwata, Hiroaki Nishikawa:
Stage-by-Stage Power Gating Circuit for Ultra-Low-Power Self-Timed Pipeline. PDPTA 2010: 596-602

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