default search action

combined dblp search
author search
venue search
publication search

ask others

"Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory ..."

Barry J. O'Sullivan et al. (2019)

> Home

Details and statistics

DOI: 10.1109/IRPS.2019.8720598

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/irps/OSullivanRRWLRC19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/irps/OSullivanRRWLRC19
Barry J. O'Sullivan, Romain Ritzenthaler, Gerhard Rzepa, Z. Wu, E. Dentoni Litta, O. Richard, T. Conard, V. Machkaoutsan, Pierre Fazan, C. Kim, Jacopo Franco, Ben Kaczer, Tibor Grasser, Alessio Spessot, Dimitri Linten, N. Horiguchi:
Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices. IRPS 2019: 1-8

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.