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"A Method for Integrating Network-on-Chip Topologies with 3D ICs."

M. Pawan Kumar et al. (2011)

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DOI: 10.1109/ISVLSI.2011.74

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/isvlsi/KumarKMBV11
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  persistent URL:
  - https://dblp.org/rec/conf/isvlsi/KumarKMBV11
M. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini, Kamakoti Veezhinathan:
A Method for Integrating Network-on-Chip Topologies with 3D ICs. ISVLSI 2011: 60-65

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