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"18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die ..."

Jong-Chern Lee et al. (2016)

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DOI: 10.1109/ISSCC.2016.7418035

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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  - https://dblp.org/rec/conf/isscc/LeeKKKKJYKCKKKO16
Jong-Chern Lee, Jihwan Kim, Kyung Whan Kim, Young Jun Ku, Dae Suk Kim, Chunseok Jeong, Tae Sik Yun, Hongjung Kim, Ho Sung Cho, Yeon Ok Kim, Jae-Hwan Kim, Jin Ho Kim, Sangmuk Oh, Hyun Sung Lee, Ki Hun Kwon, Dong Beom Lee, Young Jae Choi, Jeajin Lee, Hyeon Gon Kim, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee:
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface. ISSCC 2016: 318-319

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