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"Switch level optimization of digital CMOS gate networks."

Leomar S. da Rosa Jr. et al. (2009)

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DOI: 10.1109/ISQED.2009.4810315

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/isqed/RosaSRR09
Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis:
Switch level optimization of digital CMOS gate networks. ISQED 2009: 324-329

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