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"A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and ..."

James B. Kuo, K. W. Su, J. H. Lou (1994)

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DOI: 10.1109/ISCAS.1994.409262

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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James B. Kuo, K. W. Su, J. H. Lou:
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction Architecture and 1.5V Full-Swing BiCMOS Dynamic Logic Circuit. ISCAS 1994: 323-326

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