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"Optimized VLSI Circuit Partitioning and Testing Using ACO and BIST ..."

M. R. Ezilarasan et al. (2024)

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DOI: 10.1007/978-981-97-4399-5_35

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-20

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  dblp key:
  - conf/isnn/EzilarasanPLCD24
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  - https://dblp.org/rec/conf/isnn/EzilarasanPLCD24
M. R. Ezilarasan, D. Preethi, Man-Fai Leung, Hangjun Che, Xiangguang Dai:
Optimized VLSI Circuit Partitioning and Testing Using ACO and BIST Architectures. ISNN 2024: 372-381

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