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"Scalable instruction set simulator for thousand-core architectures running ..."

Shivani Raghav et al. (2010)

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DOI: 10.1109/HPCS.2010.5547092

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

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  - conf/ieeehpcs/RaghavRAPMB10
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  - https://dblp.org/rec/conf/ieeehpcs/RaghavRAPMB10
Shivani Raghav, Martino Ruggiero, David Atienza, Christian Pinto, Andrea Marongiu, Luca Benini:
Scalable instruction set simulator for thousand-core architectures running on GPGPUs. HPCS 2010: 459-466

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