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"An architecture and timing-driven routing algorithm for area-efficient ..."

Hanyu Liu, Xiaolei Chen, Yajun Ha (2008)

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DOI: 10.1109/FPL.2008.4630022

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Hanyu Liu, Xiaolei Chen, Yajun Ha:
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. FPL 2008: 615-618

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