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"Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep ..."

Yufei Ma et al. (2017)

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DOI: —

access: closed

type: Conference or Workshop Paper

metadata version: 2022-08-16

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  dblp key:
  - conf/fpga/MaCVS17
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  persistent URL:
  - https://dblp.org/rec/conf/fpga/MaCVS17
Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. FPGA 2017: 45-54

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