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"Combination of Hardware and Software: An Efficient AES Implementation ..."

Jingquan Ge et al. (2018)

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DOI: 10.1007/978-3-319-99073-6_10

access: closed

type: Conference or Workshop Paper

metadata version: 2018-08-13

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  dblp key:
  - conf/esorics/GeGTXLY18
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  - https://dblp.org/rec/conf/esorics/GeGTXLY18
Jingquan Ge, Neng Gao, Chenyang Tu, Ji Xiang, Zeyi Liu, Jun Yuan:
Combination of Hardware and Software: An Efficient AES Implementation Resistant to Side-Channel Attacks on All Programmable SoC. ESORICS (1) 2018: 197-217

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