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"A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning."

Hidenori Sato, Akira Onozawa, Hiroaki Matsuda (1996)

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DOI: 10.1109/EDTC.1996.494155

access: closed

type: Conference or Workshop Paper

metadata version: 2022-05-20

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  dblp key:
  - conf/date/SatoOM96
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  persistent URL:
  - https://dblp.org/rec/conf/date/SatoOM96
Hidenori Sato, Akira Onozawa, Hiroaki Matsuda:
A Balanced-Mesh Clock Routing Technique Using Circuit Partitioning. ED&TC 1996: 237-243

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