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"CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells."

Avaneendra Gupta, John P. Hayes (1997)

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DOI: 10.1145/266021.266198

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/dac/GuptaH97
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Avaneendra Gupta, John P. Hayes:
CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. DAC 1997: 452-455

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