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"Fault Simulation and Test Pattern Generation for Cross-gate Defects in ..."

Kuan-Ying Chiang et al. (2015)

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DOI: 10.1109/ATS.2015.38

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/ats/ChiangHCPL15
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  persistent URL:
  - https://dblp.org/rec/conf/ats/ChiangHCPL15
Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, James Chien-Mo Li:
Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits. ATS 2015: 181-186

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