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"A Cost Effective Test Screening Circuit for embedded SRAM with Resume ..."
Yoshisato Yokoyama et al. (2019)
- Yoshisato Yokoyama, Kenji Goto, Tomohiro Miura, Yukari Ouchi, Daisuke Nakamura, Jiro Ishikawa, Shunya Nagata, Yoshiki Tsujihashi, Yuichiro Ishii:
A Cost Effective Test Screening Circuit for embedded SRAM with Resume Standby on 110-nm SoC/MCU. A-SSCC 2019: 17-20
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