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"A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a ..."

Po-Wei Chiu et al. (2018)

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DOI: 10.1109/ASSCC.2018.8579267

access: closed

type: Conference or Workshop Paper

metadata version: 2019-01-07

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  dblp key:
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  - https://dblp.org/rec/conf/asscc/ChiuLTK18
Po-Wei Chiu, Muqing Liu, Qianying Tang, Chris H. Kim:
A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer. A-SSCC 2018: 187-190

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