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"A novel CLB architecture and circuit packing algorithm for logic-area ..."

Vivek Garg et al. (2005)

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DOI: 10.1145/1120725.1121018

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-10

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  dblp key:
  - conf/aspdac/GargCSK05
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  - https://dblp.org/rec/conf/aspdac/GargCSK05
Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti:
A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs. ASP-DAC 2005: 791-794

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