default search action

combined dblp search
author search
venue search
publication search

ask others

"A Merged Synthesis Technique for Fast Arithmetic Blocks Involving ..."

Sabyasachi Das, Sunil P. Khatri (2008)

> Home

Details and statistics

DOI: 10.1109/VLSI.2008.112

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/DasK08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/DasK08
Sabyasachi Das, Sunil P. Khatri:
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. VLSI Design 2008: 572-579

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.