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"A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS."

Osama Elhadidy et al. (2015)

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DOI: 10.1109/VLSIC.2015.7231265

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - conf/vlsic/ElhadidyRYP15
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  - https://dblp.org/rec/conf/vlsic/ElhadidyRYP15
Osama Elhadidy, Ashkan Roshan-Zamir, Hae-Woong Yang, Samuel Palermo:
A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS. VLSIC 2015: 224-

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