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Roberto R. Osorio
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2020 – today
- 2024
- [i2]Manuel de Castro, Roberto R. Osorio, Francisco J. Andujar, Rocío Carratalá-Sáez, Yuri Torres, Diego R. Llanos:
Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools. CoRR abs/2408.02758 (2024) - [i1]Manuel de Castro, Francisco J. Andújar, Roberto R. Osorio, Rocío Carratalá-Sáez, Diego R. Llanos:
Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL. CoRR abs/2409.03391 (2024) - 2023
- [j11]Manuel de Castro
, Roberto R. Osorio, David López Vilariño, Arturo González-Escribano, Diego R. Llanos
Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL. J. Supercomput. 79(9): 9866-9888 (2023) - [j10]Roberto R. Osorio
Floating Point Calculation of the Cube Function on FPGAs. IEEE Trans. Parallel Distributed Syst. 34(1): 372-382 (2023) - 2022
- [j9]Patricia González
An efficient ant colony optimization framework for HPC environments. Appl. Soft Comput. 114: 108058 (2022)
2010 – 2019
- 2019
- [j8]Roberto R. Osorio
Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors. IEEE Access 7: 56353-56366 (2019) - [c20]Javier Cereijo García
Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities. DCIS 2019: 1-6 - [c19]Javier Cereijo García
A Microprogrammed Approach for Implementing Statecharts. DSD 2019: 27-34 - 2016
- [j7]Roberto R. Osorio, Patricia González
A fast algorithm for constructing nearly optimal prefix codes. Softw. Pract. Exp. 46(10): 1299-1316 (2016) - [c18]Roberto R. Osorio:
Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model. ASAP 2016: 202-206 - 2013
- [j6]Iván Cores
Improving Scalability of Application-Level Checkpoint-Recovery by Reducing Checkpoint Sizes. New Gener. Comput. 31(3): 163-185 (2013) - [j5]Roberto R. Osorio
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J. Signal Process. Syst. 72(2): 119-132 (2013) - [c17]Angela Souto Vieites, Roberto R. Osorio
Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks. DSD 2013: 799-802 - 2012
- [c16]Roberto R. Osorio
Fast Construction of Nearly-Optimal Prefix Codes without Probability Sorting. DCC 2012: 407 - 2011
- [j4]Alejandro Nieto, Víctor M. Brea, David López Vilariño, Roberto R. Osorio
Performance analysis of massively parallel embedded hardware architectures for retinal image processing. EURASIP J. Image Video Process. 2011: 10 (2011)
2000 – 2009
- 2009
- [c15]Roberto R. Osorio
High Performance Image Processing on a Massively Parallel Processor Array. DSD 2009: 233-236 - [c14]Cesar Diaz-Resco, Alejandro Nieto, Roberto R. Osorio
A digital cellular-based system for retinal vessel-tree extraction. ECCTD 2009: 835-838 - 2008
- [c13]Roberto R. Osorio
An FPGA architecture for CABAC decoding in manycore systems. ASAP 2008: 293-298 - 2007
- [c12]Roberto R. Osorio
Entropy Coding on a Programmable Processor Array for Multimedia SoC. ASAP 2007: 222-227 - 2006
- [j3]Roberto R. Osorio, Javier D. Bruguera:
High-Throughput Architecture for H.264/AVC CABAC Compression System. IEEE Trans. Circuits Syst. Video Technol. 16(11): 1376-1384 (2006) - [c11]Roberto R. Osorio, Javier D. Bruguera:
A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. DSD 2006: 269-274 - [c10]Javier D. Bruguera, Roberto R. Osorio:
A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. DSD 2006: 407-414 - 2005
- [c9]Roberto R. Osorio, Javier D. Bruguera:
A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. DSD 2005: 298-305 - 2004
- [j2]Gauthier Lafruit, Eric Delfosse, Roberto R. Osorio, Wolfgang van Raemdonck, Vissarion Ferentinos:
View-dependent, scalable texture streaming in 3-D QoS with MPEG-4 visual texture coding. IEEE Trans. Circuits Syst. Video Technol. 14(7): 1021-1031 (2004) - [c8]Roberto R. Osorio, Javier D. Bruguera:
Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. DSD 2004: 62-69 - 2003
- [j1]Roberto R. Osorio, Bart Vanhoof:
High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression. J. VLSI Signal Process. 33(3): 267-275 (2003) - 2002
- [c7]Roberto R. Osorio, Sylvain Devillers, Eric Delfosse, Myriam Amielh, Gauthier Lafruit:
Bitstream Syntax Description Language for 3D MPEG-4 view-dependent texture streaming. ICIP (3) 2002: 17-20 - 2000
- [c6]Roberto R. Osorio, Javier D. Bruguera:
Architectures for arithmetic coding in image compression. EUSIPCO 2000: 1-4
1990 – 1999
- 1999
- [c5]Roberto R. Osorio, Javier D. Bruguera:
New model for arithmetic coding/decoding of multilevel images based on a cache memory. ICECS 1999: 697-700 - 1998
- [c4]Roberto R. Osorio, Montserrat Bóo, Javier D. Bruguera:
Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. EUROMICRO 1998: 10139- - 1997
- [c3]Roberto R. Osorio, Javier D. Bruguera:
New arithmetic coder/decoder architectures based on pipelining. ASAP 1997: 106-115 - [c2]Mercedes Peón, Roberto R. Osorio, Javier D. Bruguera:
A VLSI implementation of an arithmetic coder for image compression. EUROMICRO 1997: 591- - 1995
- [c1]Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata:
Digit On-line Large Radix CORDIC Rotator. ASAP 1995: 246-257
Coauthor Index
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last updated on 2024-10-10 21:18 CEST by the dblp team
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