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Fujio Masuoka
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2020 – today
- 2021
- [c2]Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner
, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka:
1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar. IMW 2021: 1-4
2000 – 2009
- 2008
- [j12]Takuya Kadowaki, Yoshizumi Yamakawa, Hiroki Nakamura, Yasuo Kimura, Michio Niwano, Fujio Masuoka:
A New Architecture for High-Density High-Performance SGT nor Flash Memory. IEEE Trans. Circuits Syst. II Express Briefs 55-II(6): 551-555 (2008) - 2006
- [j11]Yasue Yamamoto, Takeshi Hidaka, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka:
Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering. IEICE Trans. Electron. 89-C(4): 560-567 (2006) - 2001
- [j10]Tetsuo Endoh, Kazuhisa Sunaga, Hiroshi Sakuraba, Fujio Masuoka:
An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current. IEEE J. Solid State Circuits 36(1): 34-39 (2001) - [j9]Akira Tanabe, Masato Umetani, Ikuo Fujiwara, Takayuki Ogura, Kotaro Kataoka, Masao Okihara, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka:
0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. IEEE J. Solid State Circuits 36(6): 988-996 (2001) - [c1]Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka:
An on-chip 96.5% current efficiency CMOS linear regulator. ASP-DAC 2001: 297-301
1990 – 1999
- 1999
- [j8]Tetsuo Endoh, Katsuhisa Shinmei, Hiroshi Sakuraba, Fujio Masuoka:
New three-dimensional memory array architecture for future ultrahigh-density DRAM. IEEE J. Solid State Circuits 34(4): 476-483 (1999) - 1995
- [j7]Hirofumi Yamashita, Michio Sasaki, Shinji Ohsawa, Ryohei Miyagawa, Eiji Ohba, Keiji Mabuchi, Nobuo Nakamura, Nagataka Tanaka, Nahoko Endoh, Ikuko Inoue, Yoshiyuki Matsunaga, Yoshitaka Egawa, Yukio Endo, Tetsuya Yamaguchi, Yoshinori Iida, Akihiko Furukawa, Sohei Manabe, Yoshiki Ishizuka, Hideo Ichinose, Takako Niiyama, Hisanori Ihara, Hidetoshi Nozaki, Isamu Yanase, Naoshi Sakuma, Takeo Sakakubo, Hiroki Honda, Fujio Masuoka, Okio Yoshida, Hiroyuki Tango, Shun-ichi Sano:
A 2/3-in 2 million pixel STACK-CCD HDTV imager. IEEE J. Solid State Circuits 30(8): 881-889 (1995) - 1994
- [j6]Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara:
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. IEEE J. Solid State Circuits 29(11): 1366-1373 (1994) - 1993
- [j5]Takehiro Hasegawa, Daisaburo Takashima, Ryu Ogiwara, Masako Ohta, Shinichiro Shiratake, Takeshi Hamamoto, Takashi Yamada, Masami Aoki, Shigeru Ishibashi, Yukihito Oowaki, Shigeyoshi Watanabe, Fujio Masuoka:
An experimental DRAM with a NAND-structured cell. IEEE J. Solid State Circuits 28(11): 1099-1104 (1993) - [j4]Seiichi Aritome, Riichiro Shirota, Gertjan Hemink, Tetsuo Endoh, Fujio Masuoka:
Reliability issues of flash memory cells. Proc. IEEE 81(5): 776-788 (1993) - 1990
- [j3]Kenji Tsuchida, Yukihito Oowaki, Masako Ohta, Daisaburo Takashima, Shigeyoshi Watanabe, Kazuya Ohuchi, Fujio Masuoka:
The stabilized reference-line (SRL) technique for scaled DRAMs. IEEE J. Solid State Circuits 25(1): 24-29 (1990) - [j2]Yoshihisa Iwata, Masaki Momodomi, Tomoharu Tanaka, Hideko Oodaira, Yasuo Itoh, Ryozo Nakayama, Ryouhei Kirisawa, Seiichi Aritome, Tetsuo Endoh, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka:
A high-density NAND EEPROM with block-page programming for microcomputer applications. IEEE J. Solid State Circuits 25(2): 417-424 (1990)
1980 – 1989
- 1989
- [j1]Shigeyoshi Watanabe, Yukihito Oowaki, Yasuo Itoh, Koji Sakui, Kenji Numata, Tsuneaki Fuse, Takayuki Kobayashi, Kenji Tsuchida, Masahiko Chiba, Takahiko Hara, Masako Ohta, Fumio Horiguchi, Katsuhiko Hieda, Akihiro Nitayama, Takeshi Hamamoto, Kazunori Ohuchi, Fujio Masuoka:
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. IEEE J. Solid State Circuits 24(3): 763-770 (1989)
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