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Rajesh Inti
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2020 – today
- 2022
- [j10]Mozhgan Mansuri
, Rajesh Inti, Joe Kennedy, Junyi Qiu, Chun-Ming Hsu, Jahnavi Sharma, Hao Li
A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS. IEEE J. Solid State Circuits 57(3): 757-766 (2022) - 2021
- [c17]Rajesh Inti, Mozhgan Mansuri, Joe Kennedy, Junyi Qiu, Chun-Ming Hsu, Jahnavi Sharma, Hao Li, Bryan Casper, James E. Jaussi:
A Scalable 32-to-56Gb/s 0.56-to-1.28pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28nm CMOS. CICC 2021: 1-2
2010 – 2019
- 2019
- [j9]Sudip Shekhar
A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR. IEEE J. Solid State Circuits 54(6): 1669-1681 (2019) - 2018
- [c16]Rajesh Inti
A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS. VLSI Circuits 2018: 151-152 - 2015
- [c15]Rajesh Inti, Sudip Shekhar, Ganesh Balamurugan, James E. Jaussi, Clark Roberts, Tzu-Chien Hsueh, Bryan Casper:
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS. VLSIC 2015: 346- - [c14]Sudip Shekhar, Rajesh Inti, James E. Jaussi, Tzu-Chien Hsueh, Bryan Casper:
A 1.2-5Gb/s 1.4-2pJ/b serial link in 22nm CMOS with a direct data-sequencing blind oversampling CDR. VLSIC 2015: 350- - 2014
- [j8]Guanghua Shu, Saurabh Saxena
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits 49(4): 1036-1047 (2014) - [j7]Tawfiq Musah
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS. IEEE J. Solid State Circuits 49(12): 3079-3090 (2014) - [c13]James E. Jaussi, Ganesh Balamurugan, Sami Hyvonen, Tzu-Chien Hsueh, Tawfiq Musah
26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS. ISSCC 2014: 440-441 - [c12]Tzu-Chien Hsueh, Ganesh Balamurugan, James E. Jaussi, Sami Hyvonen, Joseph T. Kennedy, Gökçe Keskin, Tawfiq Musah
26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS. ISSCC 2014: 444-445 - 2013
- [j6]Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu:
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops. IEEE J. Solid State Circuits 48(6): 1416-1428 (2013) - 2012
- [j5]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer. IEEE J. Solid State Circuits 47(12): 2916-2927 (2012) - [c11]Karthikeyan Reddy, Sachin Rao, Rajesh Inti, Brian Young, Amr Elshazly, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC using residue-cancelling VCO-based quantizer. ISSCC 2012: 152-154 - [c10]Amr Elshazly, Rajesh Inti, Brian Young, Pavan Kumar Hanumolu:
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC. ISSCC 2012: 242-244 - [c9]Thomas Toifl, Michael Ruegg, Rajesh Inti, Christian Menolfi, Matthias Braendli
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. VLSIC 2012: 102-103 - [c8]Qadeer Khan, Amr Elshazly, Sachin Rao, Rajesh Inti, Pavan Kumar Hanumolu:
A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control. VLSIC 2012: 182-183 - [c7]Amr Elshazly, Rajesh Inti, Mrunmay Talegaonkar, Pavan Kumar Hanumolu:
A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity. VLSIC 2012: 188-189 - 2011
- [j4]Wenjing Yin, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu:
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking. IEEE J. Solid State Circuits 46(8): 1870-1880 (2011) - [j3]Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration. IEEE J. Solid State Circuits 46(12): 2759-2771 (2011) - [j2]Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu:
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance. IEEE J. Solid State Circuits 46(12): 3150-3162 (2011) - [j1]Wenjing Yin, Rajesh Inti, Amr Elshazly, Mrunmay Talegaonkar, Brian Young, Pavan Kumar Hanumolu:
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery. IEEE J. Solid State Circuits 46(12): 3163-3173 (2011) - [c6]Mrunmay Talegaonkar, Rajesh Inti, Pavan Kumar Hanumolu:
Digital clock and data recovery circuit design: Challenges and tradeoffs. CICC 2011: 1-8 - [c5]Amr Elshazly, Rajesh Inti, Wenjing Yin, Brian Young, Pavan Kumar Hanumolu:
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration. ISSCC 2011: 92-94 - [c4]Rajesh Inti, Amr Elshazly, Brian Young, Wenjing Yin, Marcel A. Kossel, Thomas Toifl, Pavan Kumar Hanumolu:
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS. ISSCC 2011: 152-154 - [c3]Rajesh Inti, Wenjing Yin, Amr Elshazly, Naga Sasidhar, Pavan Kumar Hanumolu:
A 0.5-to-2.5Gb/s reference-less half-rate digital CDR with unlimited frequency acquisition range and improved input duty-cycle error tolerance. ISSCC 2011: 438-450 - [c2]Wenjing Yin, Rajesh Inti, Amr Elshazly, Pavan Kumar Hanumolu:
A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery. ISSCC 2011: 440-442 - 2010
- [c1]Wenjing Yin, Rajesh Inti, Pavan Kumar Hanumolu:
A 1.6mW 1.6ps-rms-jitter 2.5GHz digital PLL with 0.7-to-3.5GHz frequency range in 90nm CMOS. CICC 2010: 1-4
Coauthor Index
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