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Cemil Cem Gürsoy
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- affiliation: Yeditepe University, Istanbul, Turkey
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2020 – today
- 2022
- [c9]Cemil Cem Gürsoy, Daniel Kraak, Foisal Ahmed, Mottaqiallah Taouil, Maksim Jenihhin, Said Hamdioui:
On BTI Aging Rejuvenation in Memory Address Decoders. LATS 2022: 1-6 - [i4]Cemil Cem Gürsoy, Daniel Kraak, Foisal Ahmed, Mottaqiallah Taouil, Maksim Jenihhin, Said Hamdioui:
On BTI Aging Rejuvenation in Memory Address Decoders. CoRR abs/2212.09356 (2022) - 2021
- [c8]Aneesh Balakrishnan
, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu:
Modeling Soft-Error Reliability Under Variability. DFT 2021: 1-6 - 2020
- [c7]Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Lizhou Wu, Moritz Fieback
A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs. DATE 2020: 792-797 - [i3]Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar:
New categories of Safe Faults in a processor-based Embedded System. CoRR abs/2009.11621 (2020)
2010 – 2019
- 2019
- [c6]Cemil Cem Gürsoy
New categories of Safe Faults in a processor-based Embedded System. DDECS 2019: 1-4 - [c5]Adeboye Stephen Oyeniran, Raimund Ubar
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS 2019: 1-6 - [c4]Daniel H. P. Kraak, Cemil Cem Gürsoy
Software-Based Mitigation for Memory Address Decoder Aging. LATS 2019: 1-6 - [c3]Adeboye Stephen Oyeniran, Raimund Ubar
Mixed-level identification of fault redundancy in microprocessors. LATS 2019: 1-6 - [c2]Aleksa Damljanovic, Giovanni Squillero, Cemil Cem Gürsoy
On NBTI-induced Aging Analysis in IEEE 1687 Reconfigurable Scan Networks. VLSI-SoC 2019: 335-340 - [i2]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
Mixed-level identification of fault redundancy in microprocessors. CoRR abs/1907.12325 (2019) - [i1]Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik:
High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR abs/1908.02986 (2019) - 2016
- [j2]Sezer Gören
Erratum to: Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection. J. Electron. Test. 32(1): 105-106 (2016) - [c1]Cemil Cem Gürsoy
On optimization of multi-cycle tests for test quality and application time. EWDTS 2016: 1-4 - 2015
- [j1]Sezer Gören
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection. J. Electron. Test. 31(5-6): 525-536 (2015)
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