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Shigeto Maegawa
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2010 – 2019
- 2014
- [j4]Kenichi Hatasako, Tetsuya Nitta, Masami Hane, Shigeto Maegawa:
Past and Future Technology for Mixed Signal LSI. IEICE Trans. Electron. 97-C(4): 238-244 (2014)
2000 – 2009
- 2007
- [j3]Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa:
Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation. IEICE Trans. Electron. 90-C(4): 666-674 (2007) - [j2]Fukashi Morishita
, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. 90-C(4): 765-771 (2007) - 2006
- [c3]Mitsuo Usami, Akira Sato, Hisao Tanabe, Toshiaki Iwamatsu, Shigeto Maegawa, Yuzuru Ohji:
An SOI-Based 7.5µm-Thick 0.15x0.15mm2 RFID Chip. ISSCC 2006: 1191-1200 - [c2]Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa:
High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI. PATMOS 2006: 393-402 - 2005
- [c1]Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto:
A capacitorless twin-transistor random access memory (TTRAM) on SOI. CICC 2005: 435-438
1990 – 1999
- 1997
- [j1]Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma:
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. IEEE J. Solid State Circuits 32(11): 1712-1720 (1997)
Coauthor Index
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