Slack budgeting and slack to length converting for multi-bit flip-flop merging
Abstract
In this paper we propose a flexible slack budgeting approach for post-placement multi-bit flip-flop (MBFF) merging. Our approach considers existing wiring topology and flip-flop delay changes for achieving more accurate slack budgeting. Besides, we propose a slack-to-length converting approach to translating timing slack into equivalent wire length for simplifying a merging process. We also develop a merging method to evaluate our slack budgeting approach. Our slack budgeting and MBFF merging programs are fully integrated into an industrial design flow. Experimental results show that our approach on average achieves 3.4% area saving, 50% clock tree power saving, and 5.3% total power saving.
References
[1]
R. Nair, C. L. Berman, P. S. Hauge, and E. J. Yoffa, "Generation of performance constraints for layout," IEEE Trans. Computer-Aided Design, vol. CAD-8, pp. 860--874, Aug. 1989.
[2]
H. Youssef, R. B. Lin and E. Shragowitz, "Bounds on net delays for VLSI circuits," IEEE Trans. on Circuits and Systems-II: Analog and Digital Signal Processing, VOL. 39, NO. 11, pp. 815--824, Nov. 1992.
[3]
W. K. Luk, "A fast constraint generator for timing driven layout," in ACM/IEEE Proc. 28th Design Automation Conf, pp. 626--631, 1991.
[4]
M. Sarrafzadeh, D. A. Knol, and G. E. Téllez, "A delay budgeting algorithm ensuring maximum flexibility in placement," IEEE Transactions on TCAD, Vol. 16, No. 11, pp. 1332--1341, Nov. 1997.
[5]
C. Chen, A. Srivastava, and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Transactions on VLSI Systems, vol.9, no.5, pp.616--629, Oct 2001.
[6]
E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, "Optimal integer delay budgeting on directed acyclic graphs," DAC, pp. 920--925, 2003.
[7]
S. Ghiasi, E. Bozorgzadeh, P. K. Huang, R. Jafari, and M. Sarrafzadeh, "A unified theory of timing budget management," IEEE Transactions on TCAD, Vol. 25, No. 11, pp. 2364--2375, Nov. 2006.
[8]
K. Wang and M. Marek-Sadowska, "Potential slack budgeting with clock skew optimization," ICCD, pp. 265--271, Oct. 2004.
[9]
J. Frankle, "Iterative and adaptive slack allocation for performance-driven layout and FPGA routing," in ACM/IEEE Proc. 29th Design Automation Conf, pp. 536--542, 1992.
[10]
J. Seomun, S. Paik, and Y. Shin, "Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design," ASPDAC, pp. 581--586, 2010.
[11]
E. Pakbaznia, M. Pedram, "Coarse-grain MTCMOS sleep transistor sizing using delay budgeting," DATE, pp. 385--390, 2008.
[12]
S. Liu, Y. Ma, X. Hong, and Y. Wang, "Simultaneous slack budgeting and retiming for synchronous circuits optimization," ASP-DAC, pp.49--54, Jan. 2010.
[13]
Y. Kretchmer, "Using multi-bit register inference to save area and power: the good, the bad, and the ugly," EE Times Asia, May 2001.
[14]
M. P. H. Lin, C. C. Hsu, and Y. T. Chang, "Recent research in clock power saving with multi-bit flip-flops," MWSCAS, 2011.
[15]
M. P. H. Lin, C. C. Hsu, and Y. T. Chang, "Post-placement power optimization with multi-bit flip-flops," IEEE Transactions on TCAD, vol. 30, no. 12, pp. 1870--1882, Dec. 2011
[16]
Y. T. Chang, C. C. Hsu, M. P.-H. Lin, Y., W. Tsai, and S. F. Chen, "Post-placement power optimization with multi-bit flip-flops," ICCAD, pp.218--223, Nov. 2010.
[17]
J. T. Yan and Z. W. Chen, "Construction of constrained multi-bit flip-flops for clock power reduction," International Conference on Green Circuits and Systems, pp.675--678, June 2010.
[18]
J. T. Yan and Z. W. Chen, "Routability-driven flip-flop merging process for clock power reduction," Computer Design (ICCD), 2010 IEEE International Conference on, pp. 203--208, Oct. 2010.
[19]
I. H. R. Jiang, C. L. Chang, Y. M. Yang, E. Y.-W. Tsai, L. S. F. Chen, "INTEGRA-fast multi-bit flip-flop clustering for clock power saving based on interval graphs," ISPD, pp. 115--121, 2011.
[20]
S. H. Wang, Yu-Yi Liang, T. Y. Kuo and W. K. Mak. "Power-driven flip-flop merging and relocation," ISPD, pp. 107--114, 2011.
[21]
Y. Y. Liang, T. Y. Kuo and W. K. Mak. "Power-driven flip-flop merging and relocation," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions.
[22]
S. S. Y. Liu, C. J. Lee and H. M. Chen, "Agglomerative-based flip-flop merging with signal wirelength optimization," Design, Automation & Test in Europe Conf, pp. 1391--1396, 2012.
[23]
C. Chu and Y. C. Wong, "FLUTE: Fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design," IEEE Trans. on TCAD, Vol. 27, No. 1, pp. 70--83, Jan. 2008.
Index Terms
- Slack budgeting and slack to length converting for multi-bit flip-flop merging
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Published: 18 March 2013
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