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Vivek Govindaraj
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2020 – today
- 2022
- [j2]Yizhe Hu
, Xi Chen
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. IEEE J. Solid State Circuits 57(2): 518-534 (2022) - 2021
- [j1]Jianglin Du
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. IEEE J. Solid State Circuits 56(11): 3445-3457 (2021) - [c4]Jianglin Du
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. VLSI Circuits 2021: 1-2 - 2020
- [c3]Yizhe Hu, Xi Chen
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. ISSCC 2020: 276-278
2010 – 2019
- 2019
- [c2]Vivek Govindaraj, Jianglin Du
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. APCCAS 2019: 81-84 - 2016
- [c1]François Quitin, Vivek Govindaraj, Xionghu Zhong, Wee-Peng Tay
Virtual Multi-Antenna Array for Estimating the Angle-of-Arrival of a RF Transmitter. VTC Fall 2016: 1-5
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