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Hayate Okuhara
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2020 – today
- 2024
- [j12]Francesco Conti
, Gianna Paulin
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. IEEE J. Solid State Circuits 59(1): 128-142 (2024) - [c24]Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida:
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS 2024: 1-6 - 2023
- [j11]Takuya Kojima
A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. IEEE Micro 43(1): 49-57 (2023) - [c23]Karim Ali Ahmed, Hayate Okuhara, Massimo Alioto:
55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes. ISSCC 2023: 102-103 - [c22]Francesco Conti, Davide Rossi, Gianna Paulin
A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. ISSCC 2023: 326-327 - [i4]Francesco Conti, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini:
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. CoRR abs/2305.08415 (2023) - 2022
- [c21]Takuya Kojima
Body Bias Control on a CGRA based on Convex Optimization. COOL CHIPS 2022: 1-3 - 2021
- [j10]Ahmed Elnaqib
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 156-160 (2021) - [j9]Hayate Okuhara
A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 29(10): 1800-1811 (2021) - [i3]Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi:
A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS. CoRR abs/2109.01961 (2021) - 2020
- [j8]Hesam Zolfaghari
Flexible Software-Defined Packet Processing Using Low-Area Hardware. IEEE Access 8: 98929-98945 (2020) - [c20]Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. ISCAS 2020: 1-5 - [i2]Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini:
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL. CoRR abs/2007.07654 (2020) - [i1]Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini:
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. CoRR abs/2010.04566 (2020)
2010 – 2019
- 2019
- [c19]Hideto Kayashima, Takuya Kojima
Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process. CANDAR Workshops 2019: 269-274 - [c18]Hayate Okuhara, Ryosuke Kazami, Hideharu Amano:
A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration. MCSoC 2019: 32-37 - [c17]Sayaka Terashima, Takuya Kojima
A Preliminary Evaluation of Building Block Computing Systems. MCSoC 2019: 312-319 - 2018
- [j7]Carlos Cesar Cortes Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano:
Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach. IEICE Trans. Inf. Syst. 101-D(4): 1116-1125 (2018) - [j6]Takuya Kojima
Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures. IEICE Trans. Inf. Syst. 101-D(6): 1532-1540 (2018) - [j5]Hayate Okuhara
Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3241-3254 (2018) - [j4]Keita Azegami
Body Bias Control for Renewable Energy Source with a High Inner Resistance. IEEE Trans. Multi Scale Comput. Syst. 4(4): 605-612 (2018) - [j3]Hayate Okuhara
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1254-1267 (2018) - [c16]Ryosuke Kazami, Hayate Okuhara, Hideharu Amano:
Design automation methodology of a critical path monitor for adaptive voltage controls. COOL CHIPS 2018: 1-3 - [c15]Takuya Kojima
Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping. HEART 2018: 13:1-13:6 - [c14]Akram Ben Ahmed
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC 2018: 146-153 - 2017
- [j2]Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. IEICE Trans. Inf. Syst. 100-D(12): 2828-2836 (2017) - [j1]Hayate Okuhara
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1578-1582 (2017) - [c13]Keita Azegami, Hayate Okuhara, Hideharu Amano:
Body bias control for renewable energy source with a high inner resistance. COOL Chips 2017: 1-3 - [c12]Hayate Okuhara, Akram Ben Ahmed
Leveraging asymmetric body bias control for low power LSI design. COOL Chips 2017: 1-3 - [c11]Takuya Kojima
Body bias optimization for variable pipelined CGRA. FPL 2017: 1-4 - [c10]Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano:
Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA. MCSoC 2017: 143-150 - [c9]Takuya Kojima
Glitch-aware variable pipeline optimization for CGRAs. ReConFig 2017: 1-6 - 2016
- [c8]Johannes Maximilian Kühn, Akram Ben Ahmed
MuCCRA4-BB: A fine-grained body biasing capable DRP. COOL Chips 2016: 1-3 - [c7]Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano
Body bias grain size exploration for a coarse grained reconfigurable accelerator. FPL 2016: 1-4 - [c6]Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano:
Variable pipeline structure for Coarse Grained Reconfigurable Array CMA. FPT 2016: 217-220 - 2015
- [c5]Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano:
A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. COOL Chips 2015: 1-3 - [c4]Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano:
7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. FPL 2015: 1 - [c3]Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano:
Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB. CANDAR 2015: 21-29 - [c2]Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano:
An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. ISLPED 2015: 207-212 - [c1]Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano:
A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. ReConFig 2015: 1-6
Coauthor Index
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