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José M. Quintana
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2020 – today
- 2024
- [j16]Fernando García-García
, Dae-Jin Lee
Cost-Sensitive Ordinal Classification Methods to Predict SARS-CoV-2 Pneumonia Severity. IEEE J. Biomed. Health Informatics 28(5): 2613-2623 (2024) - 2023
- [j15]Janire Portuondo-Jiménez
Clinical prediction rules for adverse evolution in patients with COVID-19 by the Omicron variant. Int. J. Medical Informatics 173: 105039 (2023) - [i1]Hristo Inouzhe, Irantzu Barrio, Paula Gordaliza, María Xosé Rodríguez-Álvarez, Itxaso Bengoechea, José María Quintana:
A study on group fairness in healthcare outcomes for nursing home residents during the COVID-19 pandemic in the Basque Country. CoRR abs/2306.09711 (2023) - 2021
- [j14]Juan Núñez
Insights Into the Dynamics of Coupled VO2 Oscillators for ONNs. IEEE Trans. Circuits Syst. II Express Briefs 68(10): 3356-3360 (2021)
2010 – 2019
- 2014
- [j13]Juan Núñez
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2238-2242 (2014) - 2013
- [j12]Juan Núñez
Novel pipeline architectures based on Negative Differential Resistance devices. Microelectron. J. 44(9): 807-813 (2013) - [c44]Juan Núñez
Novel Dynamic Gate Topology for Superpipelines in DSM Technologies. DSD 2013: 280-283 - 2012
- [c43]Juan Núñez
Bifurcation diagrams in MOS-NDR frequency divider circuits. ICECS 2012: 480-483 - [c42]Juan Núñez
Compact and Power Efficient MOS-NDR Muller C-Elements. DoCEIS 2012: 437-442 - [c41]Juan Núñez
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications. PATMOS 2012: 166-174 - 2011
- [c40]Juan Núñez
Efficient realization of RTD-CMOS logic gates. ACM Great Lakes Symposium on VLSI 2011: 387-390 - 2010
- [c39]Juan Núñez
Evaluation of RTD-CMOS Logic Gates. DSD 2010: 621-627 - [c38]Juan Núñez
Single phase MOS-NDR mobile networks. ISCAS 2010: 153-156
2000 – 2009
- 2009
- [j11]José M. Quintana
Operation Limits for RTD-Based MOBILE Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(2): 350-363 (2009) - [c37]Juan Núñez
Fast and Area Efficient Multi-input Muller C-Element based on MOS-NDR. ISCAS 2009: 1811-1814 - 2008
- [j10]Héctor Pettenghi
Using multi-threshold threshold gates in RTD-based logic design: A case study. Microelectron. J. 39(2): 241-247 (2008) - [c36]José M. Quintana
Analysis of the critical rise time in MOBILE-based circuits. ICECS 2008: 938-941 - [c35]Juan Núñez
Limits to a correct operation in RTD-based ternary inverters. ISCAS 2008: 604-607 - [c34]Héctor Pettenghi
A novel contribution to the RTD-based threshold logic family. ISCAS 2008: 2350-2353 - 2007
- [c33]Juan Núñez
Correct operation in SMOBILE-based quasi-differential quantizers. ECCTD 2007: 930-933 - [c32]Juan Núñez
Operation limits in RTD-based ternary quantizers. ACM Great Lakes Symposium on VLSI 2007: 114-119 - [c31]Héctor Pettenghi
Non Return Mobile Logic Family. ISCAS 2007: 125-128 - [c30]Juan Núñez
Limits to a Correct Evaluation in RTD-Based Quaternary Inverters. ISMVL 2007: 51 - [c29]Juan Núñez
A quasi-differential quantizer based on SMOBILE. SBCCI 2007: 251-256 - 2006
- [j9]Maria J. Avedillo
Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 334-338 (2006) - [c28]José M. Quintana
Design Guides for a Correct DC Operation in RTD-based Threshold Gates. DSD 2006: 530-536 - [c27]Juan Núñez
Limits to a Correct Evaluation in RTD-based Ternary Inverters. ICECS 2006: 403-406 - [c26]David Bol, Jean-Didier Legat, José M. Quintana
Monostable-Bistable Transition Logic Elements: Threshold Logic vs. Boolean Logic Comparison. ICECS 2006: 1049-1052 - [c25]José M. Quintana, Maria J. Avedillo, Héctor Pettenghi:
Self-latching operation limits for MOBILE circuits. ISCAS 2006 - 2005
- [j8]José M. Quintana
Analysis of frequency divider RTD circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(10): 2234-2247 (2005) - [c24]Maria J. Avedillo
Logic Models Supporting the Design of MOBILE-based RTD Circuits. ASAP 2005: 254-259 - [c23]Maria J. Avedillo
Robust frequency divider based on resonant tunneling devices. ISCAS (3) 2005: 2647-2650 - 2004
- [j7]Maria J. Avedillo
Pass-transistor based implementations of threshold logic gates for WOS filtering. Microelectron. J. 35(11): 869-873 (2004) - [j6]Maria J. Avedillo
A Practical Parallel Architecture for Stacks Filters. J. VLSI Signal Process. 38(2): 91-100 (2004) - [c22]Maria J. Avedillo
A Threshold Logic Synthesis Tool for RTD Circuits. DSD 2004: 624-627 - [c21]José M. Quintana, Maria J. Avedillo, Héctor Pettenghi:
Programmable logic gate based on resonant tunnelling devices. ISCAS (3) 2004: 697-700 - 2003
- [j5]Valeriu Beiu
VLSI implementations of threshold logic-a comprehensive survey. IEEE Trans. Neural Networks 14(5): 1217-1243 (2003) - [c20]Valeriu Beiu
Review of Capacitive Threshold Gate Implementations. ICANN 2003: 737-744 - [c19]Valeriu Beiu, José M. Quintana, Maria J. Avedillo:
Review of Differential Threshold Gate Implementations. Neural Networks and Computational Intelligence 2003: 44-49 - 2002
- [j4]Manuel Martínez, Maria José Avedillo
COPAS: A New Algorithm for the Partial Input Encoding Problem. VLSI Design 14(2): 171-181 (2002) - [c18]Manuel Martínez, Maria J. Avedillo
An Encoding Technique for Low Power CMOS Implementations of Controllers. DATE 2002: 1083 - [c17]José M. Quintana
Threshold-logic-based design of compressors. ICECS 2002: 661-664 - [c16]Esther Rodríguez-Villegas, José M. Quintana, Maria J. Avedillo, Adoración Rueda:
High-speed low-power logic gates using floating gates. ISCAS (5) 2002: 389-392 - [c15]José M. Quintana, Maria J. Avedillo, José L. Huertas:
Simplified Reed-Muller expressions for residue threshold functions. ISCAS (4) 2002: 599-602 - [c14]Maria J. Avedillo, José M. Quintana, Esther Rodríguez-Villegas:
Simple parallel weighted order statistic filter implementations. ISCAS (4) 2002: 607-610 - 2001
- [j3]José M. Quintana
Efficient Realization of a Threshold Voter for Self-Purging Redundancy. J. Electron. Test. 17(1): 69-73 (2001) - [c13]José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas:
Practical low-cost CPL implementations threshold logic functions. ACM Great Lakes Symposium on VLSI 2001: 139-144 - [c12]José M. Quintana, Maria J. Avedillo, Raúl Jiménez, Esther Rodríguez-Villegas:
Low-power logic styles for full-adder circuits. ICECS 2001: 1417-1420 - [c11]José M. Quintana
Reed-Muller descriptions of symmetric functions. ISCAS (4) 2001: 682-685 - 2000
- [j2]Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda
νMOS-based Sorter for Arithmetic Applications. VLSI Design 11(2): 129-136 (2000) - [c10]José M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda:
Efficient νMOS Realization of Threshold Voters for Self-Purging Redundancy. SBCCI 2000: 321-326
1990 – 1999
- 1999
- [c9]Manuel Martínez, Maria J. Avedillo
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length. DATE 1999: 521-525 - [c8]Esther Rodríguez-Villegas, Maria J. Avedillo, José M. Quintana, Gloria Huertas, Adoración Rueda:
vMOS-based sorters for multiplier implementations. ISCAS (1) 1999: 338-341 - 1998
- [c7]Manuel Martínez, Maria J. Avedillo
A Dynamic Model for the State Assignment Problem. DATE 1998: 835-839 - 1997
- [c6]Juan A. Prieto, Adoración Rueda, José M. Quintana, José Luis Huertas:
A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs. ED&TC 1997: 389-394 - 1995
- [j1]Maria J. Avedillo
Constrained state assignment of easily testable FSMs. J. Electron. Test. 6(1): 133-138 (1995) - [c5]José M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas:
Optimum PLA folding through boolean satisfiability. ASP-DAC 1995 - 1994
- [c4]Juan A. Prieto, José M. Quintana, Adoración Rueda, José L. Huertas:
An Algorithm for the Place-and-Route Problem in the Layout of Analog Circuits. ISCAS 1994: 491-494 - 1993
- [c3]Maria J. Avedillo, José M. Quintana, José L. Huertas:
Easily Testable PLA-based FSMS. ISCAS 1993: 1603-1606 - 1990
- [c2]Maria J. Avedillo, José M. Quintana, José Luis Huertas:
A new method for the state reduction of incompletely specified finite sequential machines. EURO-DAC 1990: 552-556
1980 – 1989
- 1988
- [c1]José L. Huertas, José M. Quintana:
A new method for the efficient state-assignment of PLA-based sequential machines. ICCAD 1988: 156-159
Coauthor Index
aka: Maria José Avedillo
aka: José L. Huertas
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