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Mikaël Cassé
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2020 – today
- 2024
- [c19]Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Joseph Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikaël Cassé, Philippe Galy:
LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching. NewCAS 2024: 65-69 - 2023
- [c18]G. Elbaz, Mikaël Cassé, V. Labracherie, G. Roussely, Benoit Bertrand, Heimanu Niebojewski, Maud Vinet, F. Balestro, Matias Urdampilleta, Tristan Meunier, Bruna Cardoso Paz:
Transport characterization of CMOS-based devices fabricated with isotopically-enriched 28Si for spin qubit applications. ESSDERC 2023: 5-8 - [c17]Quentin Berlingard, M. Moulin, J.-P. Michel, T. Fache, Ismael Charlet, C. Plantier, Z. Chalupa, Jose Lugo-Alvarez
, Jean-Pierre Raskin, Louis Hutin, Mikaël Cassé:
RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature. ESSDERC 2023: 148-151 - [c16]Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mikaël Cassé, Philippe Galy:
Noise modeling using look-up tables and DC measurements for cryogenic applications. VLSI-SoC 2023: 1-6 - 2022
- [c15]Lauriane Contamin, Mikaël Cassé, Xavier Garros, Fred Gaillard, Maud Vinet, Philippe Galy, André Juge, Emmanuel Vincent, Silvano De Franceschi, Tristan Meunier:
Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K. IRPS 2022: 7 - [c14]Tadeu Mota Frutuoso, Xavier Garros, Perrine Batude, Laurent Brunet, Joris Lacord, Benoit Sklénard, V. Lapras, Claire Fenouillet-Béranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, Edoardo Catapano, Mikaël Cassé, Jose Lugo-Alvarez, Philippe Ferrari, Fred Gaillard:
Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration. VLSI Technology and Circuits 2022: 332-333 - [c13]Heimanu Niebojewski, Benoit Bertrand, Etienne Nowak
Specificities of linear Si QD arrays integration and characterization. VLSI Technology and Circuits 2022: 415-416 - 2021
- [c12]Louis Hutin, Benoit Bertrand, Heimanu Niebojewski, Pierre-André Mortemousque, Mikaël Cassé, Gérard Billiot, Xavier Jehl
MOS technology for quantum computing: recent progress and perspectives for scaling up. DRC 2021: 1-2 - [c11]Michelly de Souza
Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors. ESSDERC 2021: 223-226 - [c10]Tadeu Mota Frutuoso
Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration. IRPS 2021: 1-5
2010 – 2019
- 2018
- [c9]Antoine Laurent, Xavier Garros, Sylvain Barraud, J. Pelloux-Prayer
Performance & reliability of 3D architectures (πfet, Finfet, Ωfet). IRPS 2018: 6 - 2017
- [j3]Bruna Cardoso Paz, Renan Trevisoli Doria, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello:
Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. Microelectron. Reliab. 79: 111-118 (2017) - [c8]Jessy Micout, Quentin Rafhay, Xavier Garros, Mikaël Cassé, Jean Coignus
Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices. ESSDERC 2017: 144-147 - 2016
- [j2]Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Olivier Faynot, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello:
Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectron. Reliab. 63: 1-10 (2016) - [c7]Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot:
Analog performance of strained SOI nanowires down to 10K. ESSDERC 2016: 222-225 - 2015
- [c6]J. Pelloux-Prayer
Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model. ESSDERC 2015: 210-213 - 2014
- [c5]François Andrieu, Mikaël Cassé, E. Baylac, P. Perreau, O. Nier, Denis Rideau, R. Berthelon, Franck Pourchon, A. Pofelski, Barbara De Salvo, C. Gallon, Vincent Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, Vincent Barral, Rossella Ranica, Nicolas Planes, Walter Schwarzenbach, E. Richard, Emmanuel Josse, Olivier Weber, Franck Arnaud, Maud Vinet, Olivier Faynot
Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. ESSDERC 2014: 106-109 - [c4]Claire Fenouillet-Béranger, Bernard Previtali, Perrine Batude, Fabrice Nemouchi, Mikaël Cassé, Xavier Garros, Lucie Tosti, Nils Rambal, Dominique Lafond, Hugo Dansas, Luca Pasini, Laurent Brunet, Fabien Deprat, Magali Grégoire, M. Mellier, Maud Vinet:
FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration. ESSDERC 2014: 110-113 - 2013
- [c3]Remi Coquand, Sylvain Barraud, Mikaël Cassé, Masahiro Koyama, Virginie Maffini-Alvaro, Marie-Pierre Samson, Lucie Tosti, Xavier Mescot, Gérard Ghibaudo, Stéphane Monfray, Frédéric Boeuf, Olivier Faynot, Barbara De Salvo:
Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations. ESSDERC 2013: 198-201 - [c2]Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Gérard Ghibaudo
Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs. ESSDERC 2013: 300-303 - 2012
- [c1]Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Hiroshi Iwai, Gérard Ghibaudo, Gilles Reimbold:
Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs. ESSDERC 2012: 73-76
2000 – 2009
- 2009
- [j1]Xavier Garros, Mikaël Cassé, M. Rafik, Claire Fenouillet-Béranger, Gilles Reimbold, François Martin, Claudia Wiemer
Process dependence of BTI reliability in advanced HK MG stacks. Microelectron. Reliab. 49(9-11): 982-988 (2009)
Coauthor Index
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