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Teresa Monreal Arnal
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2020 – today
- 2024
- [i3]Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal, José María Llabería:
Reuse Detector: Improving the Management of STT-RAM SLLCs. CoRR abs/2402.00533 (2024) - 2023
- [c11]Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Jerónimo Castrillón, Víctor Viñals:
Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs. HPCA 2023: 179-192 - [c10]Carlos Escuin, Fernando García-Redondo
, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS 2023: 1-5 - 2022
- [c9]Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, Jerónimo Castrillón:
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches. DroneSE/RAPIDO@HiPEAC 2022: 53-58 - [i2]Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals:
Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR abs/2204.03512 (2022) - [i1]Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals:
L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR abs/2204.09504 (2022) - 2021
- [j10]Javier Díaz, Pablo Ibáñez
Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. 77(10): 11756-11785 (2021)
2010 – 2019
- 2019
- [j9]Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé
A fault-tolerant last level cache for CMPs operating at ultra-low voltage. J. Parallel Distributed Comput. 125: 31-44 (2019) - [j8]Javier Díaz, Teresa Monreal
ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. 125: 106-120 (2019) - 2018
- [j7]Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro
Reuse Detector: Improving the Management of STT-RAM SLLCs. Comput. J. 61(6): 856-880 (2018) - 2016
- [j6]Alexandra Ferrerón-Labari
Concertina: Squeezing in Cache Content to Operate at Near-Threshold Voltage. IEEE Trans. Computers 65(3): 755-769 (2016) - 2014
- [j5]Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping. ACM Trans. Archit. Code Optim. 11(2): 19:1-19:26 (2014) - [c8]Alexandra Ferrerón-Labari, Darío Suárez Gracia
Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. SBAC-PAD 2014: 238-245 - 2012
- [j4]Darío Suárez Gracia
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1510-1523 (2012)
2000 – 2009
- 2009
- [c7]Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals:
Light NUCA: A proposal for bridging the inter-cache latency gap. DATE 2009: 530-535 - 2008
- [c6]Jesús Alastruey
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD 2008: 63-70 - 2007
- [c5]Jesús Alastruey
Microarchitectural Support for Speculative Register Renaming. IPDPS 2007: 1-10 - 2006
- [c4]Jesús Alastruey
Speculative early register release. Conf. Computing Frontiers 2006: 291-302 - 2005
- [j3]Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero:
Hardware support for early register release. Int. J. High Perform. Comput. Netw. 3(2/3): 83-94 (2005) - 2004
- [j2]Teresa Monreal
Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers 53(10): 1244-1259 (2004) - 2002
- [c3]Teresa Monreal
Hardware Schemes for Early Register Release. ICPP 2002: 5-13 - 2000
- [j1]Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism 2 (2000)
1990 – 1999
- 1999
- [c2]Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO 1999: 186-192 - 1997
- [c1]Antonio González, Mateo Valero, José González, Teresa Monreal Arnal:
Virtual registers. HiPC 1997: 364-369
Coauthor Index
aka: Víctor Viñals Yúfera
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