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Michael Shebanow
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2010 – 2019
- 2016
- [j3]Pavel Krajcevski, Abhinav Golas, K. Ramani, Michael Shebanow, Dinesh Manocha:
VBTC: GPU-Friendly Variable Block Size Texture Encoding. Comput. Graph. Forum 35(2): 409-418 (2016) - [j2]Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe:
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro 36(4): 70-85 (2016) - 2013
- [c11]Michael Shebanow:
Peta Thread Computing [Keynote I]. ISPASS 2013: 1 - 2011
- [c10]Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt:
Improving GPU performance via large warps and two-level warp scheduling. MICRO 2011: 308-317
2000 – 2009
- 2009
- [c9]Michael Shebanow:
Pervasive massively multithreaded GPU processors. Conf. Computing Frontiers 2009: 227
1990 – 1999
- 1995
- [c8]Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey:
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. ISCA 1995: 151-162 - 1991
- [c7]Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow:
Single Instruction Stream Parallelism is Greater Than Two. ISCA 1991: 276-286
1980 – 1989
- 1988
- [c6]Stephen W. Melvin, Michael Shebanow, Yale N. Patt:
Hardware support for large atomic units in dynamically scheduled machines. MICRO 1988: 60-63 - 1987
- [j1]Alvin M. Despain, Yale N. Patt, Vason P. Srini, Philip Bitar, William R. Bush, C. Chien, Wayne Citrin, Barry Fagin, Wenwei Hwu, Stephen W. Melvin, Rick McGeer, Ashok Singhal, Michael Shebanow, Peter Van Roy:
Aquarius. SIGARCH Comput. Archit. News 15(1): 22-34 (1987) - [c5]James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt:
On tuning the microarchitecture of an HPS implementation of the VAX. MICRO 1987: 162-167 - 1986
- [c4]Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Chein Chen, Jiajuin Wei:
Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. COMPCON 1986: 254-258 - [c3]Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow, Chein Chen:
Run-time generation of HPS microinstructions from a VAX instruction stream. MICRO 1986: 75-81 - 1985
- [c2]Yale N. Patt, Wen-mei W. Hwu, Michael Shebanow:
HPS, a new microarchitecture: rationale and introduction. MICRO 1985: 103-108 - [c1]Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow:
Critical issues regarding HPS, a high performance microarchitecture. MICRO 1985: 109-116
Coauthor Index
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