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Microelectronics Journal, Volume 83
Volume 83, January 2019
- Sheng-Lyang Jang, Yi-You Liu, Miin-Horng Juang:
A triple-band voltage-controlled oscillator with a triple-resonance resonator. 1-5 - Iman Fattahi
, Hamid Reza Mirdamadi
A novel 3D skeletal frame topology for energy harvesting systems. 6-17 - Farnaz Khamin-Hamedani
Design of low phase-noise oscillators based on microstrip triple-band bandpass filter using coupled lines resonator. 18-26 - Yang Liu
Electromagnetic modeling and analysis of the tapered differential through glass vias. 27-31 - Di Li, Chunlong Fei, Xiaopeng Wu, Yintang Yang:
A 6-bit digital CMOS variable gain attenuator with large dynamic range and high linearity-in-dB for ultrasound imaging applications. 32-38 - Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu:
Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices. 39-49 - Alireza Kokabi, Hamidreza Ghanbari Khorram:
Bandwidth and gain enhancement using nested cross-coupled positive feedback. 50-61 - Rodrigo A. S. Braga
A 0.25-V calibration-less inverter-based OTA for low-frequency Gm-C applications. 62-72 - Sergey Podryadchikov, Vadim Putrolaynen, Maksim Belyaev
FPGA-based testing system of NAND-memory multi-chip modules. 73-76 - Mohan Julien, Serge Bernard
Breaking the speed-power-accuracy trade-off in current mirror with non-linear CCII feedback. 77-85 - Engin Afacan:
Inversion coefficient optimization based Analog/RF circuit design automation. 86-93 - Ahmet Abaci, Erkan Yüce:
Single DDCC based new immittance function simulators employing only grounded passive elements and their applications. 94-103 - Xin Xin, Jueping Cai, Teng Teng Chen, Qi Di Yang:
A 0.4-V 10-bit 10-KS/s SAR ADC in 0.18 μm CMOS for low energy wireless senor network chip. 104-116 - Asgar Abbaszadeh
Low complexity digital background calibration algorithm for the correction of timing mismatch in time-interleaved ADCs. 117-125 - Hussain Mohammed Dipu Kabir
Polycrystalline transistor with multiple thresholds. 126-130 - Chunxiao Fan, Fu Li, Xin Cao, Biao Qian, Peipei Song:
A parallel arithmetic for hardware realization of digital filters. 131-136 - Keni Qiu, Yujie Zhu, Yuanchao Xu, Qirun Huo, Chun Jason Xue:
BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. 137-146 - Mohamed Chentouf
Power aware setup timing optimization in physical design of ASICs. 147-154 - Panagiotis Bertsias
Design and application examples of CMOS fractional-order differentiators and integrators. 155-167 - Sherif M. Sharroush:
A predischarged bitline 1T-1C DRAM readout scheme. 168-184 - Jian-De Li, Chun-Hao Kuo, Guan-Ruei Lu
Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochips. 185-196 - Maryam Gharaei Jomehei
A low-power low-noise CMOS bio-potential amplifier for multi-channel neural recording with active DC-rejection and current sharing. 197-211
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