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Microprocessors and Microsystems, Volume 31
Volume 31, Number 1, February 2007
- Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis:
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. 1-14 - Jung-Hi Min, Hojung Cha, Vason P. Srini:
Dynamic power management of DRAM using accessed physical addresses. 15-24 - Ming Z. Zhang, Hau T. Ngo, Vijayan K. Asari:
Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution. 25-37 - Shehryar Shaheen, Donal Heffernan, Gabriel Leen
:
A gateway for time-triggered control networks. 38-50 - Rama Sangireddy:
Register port complexity reduction in wide-issue processors with selective instruction execution. 51-62 - Jong Wook Kwak
Dynamic per-branch history length adjustment to improve branch prediction accuracy. 63-76
Volume 31, Number 2, March 2007
- J. Morris Chang, C. Dan Lo:
FPGA-based reconfigurable computing II. - Javier Castillo, Pablo Huerta, José Ignacio Martínez:
Secure IP downloading for SRAM FPGAs. 77-86 - Steven W. Alexander, Eugen Pfann, Robert W. Stewart:
An improved algorithm for assessing the overall quantisation error in FPGA based CORDIC systems computing a vector magnitude. 87-93 - Ming-Haw Jing, Zih-Heng Chen, Jian-Hong Chen, Yan-Haw Chen:
Reconfigurable system for high-speed and diversified AES using FPGA. 94-102 - Chuan He, Guan Qin, Mi Lu, Wei Zhao
Optimized high-order finite difference wave equations modeling on reconfigurable computing platform. 103-115 - Alex K. Jones
An automated, FPGA-based reconfigurable, low-power RFID tag. 116-134 - Tom Van Court, Martin C. Herbordt:
Families of FPGA-based accelerators for approximate string matching. 135-145 - Richard B. Kujoth, Chi-Wei Wang, Jeffrey J. Cook, Derek B. Gottlieb, Nicholas P. Carter:
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor. 146-159 - Dimitrios K. Iakovidis
FPGA architecture for fast parallel computation of co-occurrence matrices. 160-165
Volume 31, Number 3, May 2007
- Veerle Desmet, Hans Vandierendonck
Clustered indexing for branch predictors. 168-177 - Hua Yang, Gang Cui, Hongwei Liu, Xiao-Zong Yang:
Compacting register file via 2-level renaming and bit-partitioning. 178-187 - Kyriakos Vlachos, Theofanis Orphanoudakis, Ioannis Papaefstathiou, Nikos A. Nikolaou, Dionisios N. Pnevmatikatos
Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for high-speed network processors units. 188-199 - Hou Rui, Longbing Zhang, Weiwu Hu:
Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread. 200-211
Volume 31, Number 4, June 2007
- Paolo Bellavista
Special Issue with selected papers from the 11th IEEE Symposium on Computers and Communications (ISCC'06). 213-214 - Mikaël Morelle, Claire Goursaud, Anne Julien-Vergonjanne, Christelle Aupetit-Berthelemot, Jean-Pierre Cances, Jean-Michel Dumas, Philippe Guignard:
2-Dimensional optical CDMA system performance with parallel interference cancellation. 215-221 - Joel Sommers, Paul Barford, Walter Willinger:
Laboratory-based calibration of available bandwidth estimation tools. 222-235 - Carlos Miguel Tavares Calafate
A distributed admission control system for MANET environments supporting multipath routing protocols. 236-251 - Jamal N. Al-Karaki, Ghada A. Al-Mashaqbeh:
Energy-centric routing in wireless sensor networks. 252-262 - John C. McEachen, Cheng Kah Wai:
An analysis of distributed sensor data aggregation for network intrusion detection. 263-272 - Giuseppe Di Fatta
Decentralized load balancing for highly irregular search problems. 273-281
Volume 31, Number 5, August 2007
- Eero Aho, Jarno Vanne
Configurable implementation of parallel memory based real-time video downscaler. 283-292 - Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin:
Reducing non-deterministic loads in low-power caches via early cache set resolution. 293-301 - Darrin M. Hanna
Executing large algorithms on low-capacity FPGAs using flowpath partitioning and runtime reconfiguration. 302-312 - Andrej Zemva, Matjaz Verderber:
FPGA-oriented HW/SW implementation of the MPEG-4 video decoder. 313-325 - Devaraj Ayavoo, Michael J. Pont, Michael Short
Two novel shared-clock scheduling algorithms for use with 'Controller Area Network' and related protocols. 326-334 - A. Jameel, Mohammed Yakoob Siyal, N. Ahmed:
Transform-domain and DSP based secure speech communication system. 335-346 - Nikolaos Kavvadias, Vasiliki Giannakopoulou, Spiridon Nikolaidis
Development of a customized processor architecture for accelerating genetic algorithms. 347-359 - Linda E. M. Brackenbury, Wei Shao:
Lowering power in an experimental RISC processor. 360-368
Volume 31, Number 6, September 2007
- Steve Liu:
Special Issue on Sensor Systems. 369 - R. A. Siddiqui, W. Amer, Qaisar Ahsan, Roger I. Grosvenor, Paul W. Prickett
Multi-band infinite impulse response filtering using microcontrollers for e-Monitoring applications. 370-380 - Georgios P. Mazarakis, John N. Avaritsiotis:
Vehicle classification in Sensor Networks using time-domain signal processing and Neural Networks. 381-392 - Jesús Ureña
Advanced sensorial system for an acoustic LPS. 393-401 - Ajay Kumar, Sankar Sarkar, Rajendra Prasad Agarwal:
A novel algorithm and FPGA based adaptable architecture for correcting sensor non-uniformities in infrared system. 402-407 - Fabrice Aubépart, Nicolas H. Franceschini:
Bio-inspired optic flow sensors based on FPGA: Application to Micro-Air-Vehicles. 408-419 - Abhiman Hande, Todd Polk, William P. Walker, Dinesh K. Bhatia
Indoor solar energy harvesting for sensor network router nodes. 420-432
Volume 31, Number 7, November 2007
- Younes Lahbib, Meriam Kallel, Ayoub Dhouib, Maher Hechkel, Antoine Perrin, Rached Tourki:
System on Chips optimization using ABV and automatic generation of SystemC codes. 433-444 - Hamid Hashemi-Najafabadi, Hamid Sarbazi-Azad, Pedram Rajabzadeh:
An accurate performance model of fully adaptive routing in wormhole-switched two-dimensional mesh multicomputers. 445-455 - Yuan-Yang Zhang, Zheng Li, Lei Yang, Shao-Wu Zhang:
An efficient CSA architecture for montgomery modular multiplication. 456-459 - Lorenzo Colitti, Giuseppe Di Battista
Investigating prefix propagation through active BGP probing. 460-474
Volume 31, Number 8, December 2007
- Chia-Tien Dan Lo, J. Morris Chang:
FPGA-based reconfigurable computing III. 475-476 - Sherif M. Saif, Hazem M. Abbas
An FPGA implementation of a neural optimization of block truncation coding for image/video compression. 477-486 - Luciano Volcan Agostini
Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs. 487-497 - Miguel A. Vega-Rodríguez
Reconfigurable computing system for image processing via the internet. 498-515 - Wen-Jyi Hwang, Wen-Kang Wei, Yao-Jung Yeh:
FPGA implementation of full-search vector quantization based on partial distance search. 516-528 - Chau-Yun Hsu, Tsung Sheng Kuo, Yuan Hung Hsu:
Low complexity radix-4 butterfly design for the soft-decision Viterbi decoder. 529-536 - Jérémie Detrey, Florent de Dinechin:
Parameterized floating-point logarithm and exponential functions for FPGAs. 537-545 - Reid B. Porter, Jan R. Frigo, Al Conti, Neal R. Harvey
A reconfigurable computing framework for multi-scale cellular image processing. 546-563
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