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Journal of Low Power Electronics, Volume 11
Volume 11, Number 1, March 2015
- Esmaeil Amini, Zahra Jeddi, Ahmed K. F. Khattab, Magdy A. Bayoumi:
Performance Evaluation and Design Optimization for Flexible Multiple Instruction Multiple Data Elliptic Curve Cryptography Crypto Architecture. 1-15 - Sumanta Pyne, Ajit Pal:
Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating. 16-36 - Himani Upadhyay, Shubhajit Roy Chowdhury:
A High Speed and Low Power 8 Bit × 8 Bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates. 37-48 - Nandakishor Yadav
, Manisha Pattanaik, G. K. Sharma:
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET. 49-62 - A. Allaoui, Azzedine Hamid, Pierre Spitéri, Vincent Bley, Thierry Lebey
Thermal Modeling of an Integrated Inductor in a Micro-Converter. 63-73 - Alexandre Huffenus, Gaël Pillonnet
Digitally Assisted Analog: An Anti-Clipping Function for Class-D Audio Amplifier. 74-83 - Remy Cellier, Pawel Fiedorow:
A 0.35 um CMOS Operational Amplifier Using Multi-Path Frequency Compensation. 84-92 - Maher Assaad
A 3-Bit Pseudo Flash ADC Based Low-Power CMOS Interface Circuit Design for Optical Sensor. 93-102
Volume 11, Number 2, June 2015
- Savithra Eratne, Pradeep S. Nair, Eugene John
A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors. 103-111 - Dieudonne Manzi Mugisha, Hu Chen, Sanghamitra Roy
Resilient Cache Design for Mobile Processors in the Near-Threshold Regime. 112-120 - Bharat Garg, G. K. Sharma:
PAID: Process Aware Imprecise DCT Architecture Trading Quality for Energy Efficiency. 121-132 - Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti:
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. 133-148 - Sumanta Pyne, Ajit Pal:
Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence. 149-172 - Shaahin Angizi
An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder. 173-180 - Venkatachalam Nithish Kumar
An Improved Reconfigurable Finite Impulse Response Filter Using Common Subexpression Elimination Algorithm for Cognitive Radio. 181-189 - Anna Richelli
A 30 mV-2.5 V DC/DC Converter for Energy Harvesting. 190-195 - Benoit Labbe, Bruno Allard:
An On-Board Step-Down DC/DC Converter for System-On-Chip Power-Supply Strategy. 196-207 - Miguel D. Fernandes
Wideband CMOS Receiver with Integrated Filtering and a Current-Mode Sigma-Delta Analog-to-Digital Converter. 208-216 - Jian-Jun Song, He Zhu, Chao Yang, Li-Xia Zhao, He-Ming Zhang:
An Optimized Super-Junction VDMOS with Breakdown Voltage Over 600 V. 217-224 - Vikas Mahor, Manisha Pattanaik:
Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic. 225-235 - Leonardo Steinfeld, Julian Oreggioni
Smart Coulomb Counter for Self-Metering Wireless Sensor Nodes Consumption. 236-248 - Nadine Azémard, Eugeni García-Moreno:
Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014. 249 - Esteve Amat
Variability Influence on FinFET-Based On-Chip Memory Data Paths. 250-255 - Guillermo Indalecio Fernández, Natalia Seoane
Variability Characterisation of Nanoscale Si and InGaAs Fin Field-Effect-Transistors at Subthreshold. 256-262
Volume 11, Number 3, September 2015
- Hao Shen, Qinru Qiu:
Chip Multiprocessor Performance Modeling for Contention Aware Task Migration and Frequency Scaling. 263-277 - Péter Horváth, Gábor Hosszú
ARTL-Based Hardware Synthesis to Non-Heterogeneous Standard Cell ASIC Technologies. 278-289 - A. Jasuja, R. K. Sharma:
A Design Approach for Efficient Multipliers for Wearable Technology. 290-297 - Pooja Joshi, Saurabh Khandelwal
Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL. 298-307 - Konstantina Roumelioti, Georgia Tsirimokou, Costas Psychalinos
Ultra-Low Voltage Analog Pre-Processing Stage for Realizing the Pan-Tompkins Algorithm. 308-315 - K. P. Pradhan, Sushanta Kumar Mohapatra
Design Equivalent Scaling on Double Gate FinFET Towards Analog and RF Figures of Merits: A Technology Computer Aided Design Estimation. 316-322 - Leonid Mats, Marlin H. Mickle, Ziqun Zhou, Joshua R. Stachel, Kara Bocan, Nicholas G. Franconi, Michael A. Rothfuss, Lee Berger, Tim Butler, Chris Ubinger, Scott Lauer, Vyasa Sai, Ervin Sejdic:
A Paradigm Shift in Passive Radio Frequency Identification Tag Development and Manufacturing Flexibility to Provide Active Tag Functionality. 323-332 - Moumita Chakraborty, Krishnendu Guha
Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications. 333-339 - João Casaleiro
Amplitude and Quadrature Errors of Two-Integrator Oscillator. 340-348 - Mohamad Al Kadi Jazairli, Denis Flandre
A 65 nm CMOS Ultra-Low-Power Impulse Radio-Ultra-Wideband Emitter for Short-Range Indoor Localization. 349-358 - Ankur Goel, Rajender K. Sharma, Anil K. Gupta:
Replica Tracked Post Silicon Trimming Enabled Negative Bit Line Voltage Based Write Assist Scheme in SRAM Design. 359-365 - Sanjit Kumar Swain, Sarosij Adak, Bikash Sharma
Effect of Channel Thickness and Doping Concentration on Sub-Threshold Performance of Graded Channel and Gate Stack DG MOSFETs. 366-372 - Jimson Mathew, Hafizur Rahaman
Selected Articles from the IEEE ISED 2014 Conference. 373-374 - Sudip Ghosh, Arijit Biswas, Santi Prasad Maity, Hafizur Rahaman
Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications. 375-386 - Naresh Vemishetty, Arpit Jain
A Robust Reliable and Low Complexity on Chip f-QRS Detection and Identification Architecture for Remote Personalized Health Care Applications. 387-400 - Bijoy Antony Jose, Abhishek Agrawal:
Improving Energy Efficiency of Virtual Machines with Timer Tick Variations. 401-405 - Rahul Shrestha, Roy P. Paily
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder. 406-412 - Priyankar Talukdar:
Power-Aware Automated Pipelining of Combinational Circuits. 413-425 - S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. 426-435 - D. N. Jagadish, M. S. Bhat
Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter. 436-443 - Chikku Abraham
A Multiple Input Variable Output Switched Capacitor DC-DC Converter for Harnessing Renewable Energy and Powering LEDs. 444-454
Volume 11, Number 4, December 2015
- Maddu Karunaratne, Assim Sagahyroon:
A Dynamic Power Estimation Method for System on Chip Designs. 455-466 - Arindam Banerjee
The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics. 467-478 - Imayavaramban Munuswamy, Patrick W. Wheeler
Electrical Braking in Matrix Converter for More Electric Aircraft: Bi-Directional Switch and Input Power Clamp Methods. 479-490 - Sangeeta Singh, Pravin Neminath Kondekar, Pawan Pal:
Non-Hysteretic Behavior of Super Steep Ferroelectric Negative Capacitance Tunnel Field Effect Transistor Based on Body Profile Engineering. 491-497 - Carmelo Zuccarotto, Anna Richelli
Design of a Low Voltage High Symmetrical Slew Rate Opamp Based on Self Cascode in UMC 0.18 μm. 498-503 - Xiang Wu, Fangming Deng, Yigang He, Bing Li:
An Ultra-Low Power CMOS Temperature Sensor for Passive RFID Application. 504-508 - Atanu Kundu
Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications. 509-516 - Carlos Leong, Jorge Semião
Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling. 517-527 - Senling Wang, Yasuo Sato, Seiji Kajihara, Hiroshi Takahashi:
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip. 528-540 - Palanichamy Manikandan
Selective Algorithms for Built-In Self-Test and Self-Diagnosis in Embedded SRAMS. 541-551
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