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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 7
Volume 7, Number 1, January 1988
- Hideo Fujiwara:
A design of programmable logic arrays with random pattern-testability. 5-10 - Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs:
Methodologies for testing embedded content addressable memories. 11-20 - Shek-Wayne Chan, Chin-Long Wey:
The design of concurrent error diagnosable systolic arrays for band matrix multiplications. 21-37 - Larry Carter, Leendert M. Huisman, Tom W. Williams:
TRIM: testability range by ignoring the memory. 38-49 - Dick L. Liu, Edward J. McCluskey:
Design of large embedded CMOS PLAs for built-in self-test. 50-59 - Shambhu J. Upadhyaya, Kewal K. Saluja:
A new approach to the design of built-in self-testing PLAs for high fault coverage. 60-67 - Edward J. McCluskey, Samy Makar, Samiha Mourad, Kenneth D. Wagner:
Probability models for pseudorandom test sequences. 68-74 - Tom W. Williams, Wilfried Daehn, Matthias Gruetzner, Corot W. Starke:
Bounds and analysis of aliasing errors in linear feedback shift registers. 75-83 - Kazuhiko Iwasaki:
Analysis and proposal of signature circuits for LSI testing. 84-90 - Laung-Terng Wang, Edward J. McCluskey:
Hybrid designs generating maximum-length sequences. 91-99 - Joseph L. A. Hughes:
Multiple fault detection using single fault test sets. 100-108 - Niraj K. Jha:
Testing for multiple faults in domino-CMOS logic circuits. 109-116 - Ronald J. Cosentino:
Concurrent error correction in systolic architectures. 117-125 - Michael H. Schulz, Erwin Trischler, Thomas M. Sarfert:
SOCRATES: a highly efficient automatic test pattern generation system. 126-137 - Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland:
Logic design verification via test generation. 138-148
Volume 7, Number 2, February 1988
- Joachim Pelka, K. P. Muller, Hermann Mader:
Simulation of dry etch processes by COMPOSITE. 154-159 - K. Lee, Andrew R. Neureuther:
SIMPL-2: (SIMulated Profiles from the Layout-Version 2). 160-167 - Francisco A. Leon:
Numerical modeling of glass flow and spin-on planarization. 168-173 - Gerhard Hobler
, Siegfried Selberherr
Two-dimensional modeling of ion implantation induced point defects. 174-180 - Mark E. Law, Robert W. Dutton:
Verification of analytic point defect models using SUPREM-IV [dopant diffusion]. 181-190 - Michael R. Kump, Robert W. Dutton:
The efficient simulation of coupled point defect and impurity diffusion. 191-204 - Ettore Landi, Paul G. Carey, Thomas W. Sigmon:
Numerical simulation of the gas immersion laser doping (GILD) process in silicon. 205-214 - Thye-Lai Tung, Jerome Connor, Dimitri A. Antoniadis:
A boundary element method for modeling viscoelastic flow in thermal oxidation. 215-224 - Mayumi Hirose, Jiro Yoshida, Nobuyuki Toyoda:
An improved two-dimensional simulation model (MEGA) for GaAs MESFET applicable to LSI design. 225-230 - Alessandro Forghieri, Roberto Guerrieri, Paolo Ciampolini, Antonio Gnudi
A new discretization strategy of the semiconductor equations comprising momentum and energy balance. 231-242 - Ross A. Williams, Deva N. Pattanayak:
ADAM: a two dimensional, two-carrier MOSFET simulator based on generalized stream functions. 243-250 - Christian A. Ringhofer, Christian Schmeiser
A modified Gummel method for the basic semiconductor device equations. 251-253 - Masaaki Tomizawa, Kiyoyuki Yokoyama, Akira Yoshii:
Nonstationary carrier dynamics in quarter-micron Si MOSFETs. 254-258 - Enrico Sangiorgi, Bruno Riccò, Franco Venturi:
MOS2: an efficient MOnte Carlo Simulator for MOS devices. 259-271 - Antonio R. Alvarez, Behrooz L. Abdi, Dennis L. Young, Harrison D. Weed, Jim Teplik, Eric R. Herald:
Application of statistical design and response surface methods to computer-aided VLSI device design. 272-288 - Mario Pinto-Guedes, Philip C. Chan:
A circuit simulation model for bipolar-induced breakdown in MOSFET. 289-294 - Erich Barke:
Line-to-ground capacitance calculation for VLSI: a comparison. 295-298 - Vered Marash, Robert W. Dutton:
Methodology for submicron device model development. 299-306 - William M. Coughran Jr., Mark R. Pinto, R. Kent Smith:
Computation of steady-state CMOS latchup characteristics. 307-323
Volume 7, Number 3, March 1988
- Sunil D. Sherlekar, P. S. Subramanian:
Conditionally robust two-pattern tests and CMOS design for testability. 325-332 - Sheldon B. Akers:
A parity bit signature for exhaustive testing. 333-338 - Hung Chi Lai, Saburo Muroga:
Design of MOS networks in single-rail input logic for incompletely specified functions. 339-345 - Hans-Jörg Mathony, Utz G. Baitinger:
CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits. 346-355 - Nohbyung Park, Alice C. Parker:
Sehwa: a software package for synthesis of pipelines from behavioral specifications. 356-370 - Shmuel Wimer, Israel Koren:
Analysis of strategies for constructive general block placement. 371-377 - Amir Alon, Uri M. Ascher:
Model and solution strategy for placement of rectangular blocks in the Euclidean plane. 378-386 - Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic:
Parallel standard cell placement algorithms with quality equivalent to simulated annealing. 387-396 - Rob A. Rutenbar
Systolic routing hardware: performance evaluation and optimization. 397-410 - Musaravakkam S. Krishnan, John P. Hayes:
A normalized-area measure for VLSI layouts. 411-419 - Teofilo F. Gonzalez, Shashishekhar Kurki-Gowdara:
Minimization of the number of layers for single row routing with fixed street capacity. 420-424 - R. J. McDonald, Jerry G. Fossum:
High-voltage device modeling for SPICE simulation of HVIC's. 425-432
Volume 7, Number 4, April 1988
- Jian-Ning Song, Yun-Kang Chen:
Two-stage channel routing for CMOS gate arrays. 439-450 - Wayne H. Wolf, Robert G. Mathews, John A. Newkirk, Robert W. Dutton:
Algorithms for optimizing, two-dimensional symbolic layout compaction. 451-466 - Sartaj K. Sahni, San-Yuan Wu:
Two NP-hard interchangeable terminal problems. 467-472 - Surendra Nahar, Sartaj K. Sahni:
Fast algorithm for polygon decomposition. 473-483 - Allan Silburt, A. R. Boothroyd, M. Digiovanni:
Automated parameter extraction and modeling of the MOSFET below threshold. 484-488 - Christian H. Corbex, Anne F. Gerodelle, Serge P. Martin, Alain R. Poncet:
Data structuring for process and device simulations. 489-500 - William Nye, David C. Riley, Alberto L. Sangiovanni-Vincentelli
DELIGHT.SPICE: an optimization-based system for the design of integrated circuits. 501-519 - Bing J. Sheu, Wen-Jay Hsu, P. K. Ko:
An MOS transistor charge model for VLSI design. 520-527 - Chin-Long Wey:
On yield consideration for the design of redundant programmable logic arrays. 528-535 - M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia:
Allocation of multiport memories in data path synthesis. 536-540 - Jerry G. Fossum, Surya Veeraraghavan, Dan Fitzpatrick:
Model selection for SOI MOSFET circuit simulation. 541-544
Volume 7, Number 5, May 1988
- Albert Seidl, Helmut Klose, Milos Svoboda, Joachim Oberndorfer, Wolfgang Rösner:
CAPCAL-a 3-D capacitance solver for support of CAD systems. 549-556 - James A. Barby, Jirí Vlach, Kishore Singhal:
Polynomial splines for MOSFET model approximation. 557-566 - Ernst Christen, Jirí Vlach:
NETOPT-a program for multiobjective design of linear networks. 567-577 - Chang G. Hwang, Robert W. Dutton:
Hot carrier transport effect in Schottky-barrier diode grown by MBE. 578-583 - John P. Robinson, Nirmal R. Saxena:
Simultaneous signature and syndrome compression. 584-589 - Gopal Gupta, Niraj K. Jha:
A universal test set for CMOS circuits. 590-597 - André Ivanov, Vinod K. Agarwal:
Dynamic testability measures for ATPG. 598-608 - Wei-Kang Huang, Fabrizio Lombardi:
On an improved design approach for C-testable orthogonal iterative arrays. 609-615 - Gary D. Hachtel, Reily M. Jacoby:
Verification algorithms for VLSI synthesis. 616-640 - Gregory J. Fisher:
An enhanced power meter for SPICE2 circuit simulation. 641-643
Volume 7, Number 6, June 1988
- Dale E. Hocevar, Paul F. Cox, Ping Yang:
Parametric yield optimization for MOS circuit blocks. 645-658 - Genhong Ruan, Jirí Vlach, James A. Barby:
Current-limited switch-level timing simulator for MOS logic networks. 659-667 - Bernhard E. Boser, Klaus-Peter Karmann, Horst Martin, Bruce A. Wooley:
Simulating and testing oversampled analog-to-digital converters. 668-674 - Shinji Odanaka, Hiroyuki Umimoto, Mutsuko Wakabayashi, Hideya Esaki:
SMART-P: rigorous three-dimensional process simulator on a supercomputer. 675-683 - James P. Cohoon, Patrick L. Heck:
BEAVER: a computational-geometry-based tool for switchbox routing. 684-697 - Douglas Braun, Jeffrey L. Burns, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli
Techniques for multilayer channel routing. 698-712 - Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton:
On the verification of sequential machines at differing levels of abstraction. 713-722 - Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli
Multi-level logic minimization using implicit don't cares. 723-740
Volume 7, Number 7, July 1988
- Steven G. Duvall:
An interchange format for process and device simulation. 741-754 - Roberto Guerrieri, Andrew R. Neureuther:
Simulation of microcrack effects in dissolution of positive resist exposed by X-ray lithography. 755-764 - Sun Young Hwang, Tom Blank, Kiyoung Choi:
Fast functional simulation: an incremental approach. 765-774 - Corrado Pedron, André Stauffer:
Analysis and synthesis of combinational pass transistor circuits. 775-786 - Salim U. Chowdhury, Melvin A. Breuer:
Optimum design of IC power/ground nets subject to reliability constraints. 787-796 - Takao Asano:
Generalized Manhattan path algorithm with applications. 797-804 - Shervin Hojat, Richard Y. Kain:
On the simplification of a placement problem. 805-812 - Henry Cox, Janusz Rajski:
A method of fault analysis for test generation and fault diagnosis. 813-833
Volume 7, Number 8, August 1988
- Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman:
SLS-a fast switch-level simulator [for MOS]. 838-849 - K. Garwacki:
Extraction of BJT model parameters using optimization method. 850-854 - Jan J. H. van der Biesen, Toru Toyabe:
Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices. 855-861 - J. Gregory Rollins, John Choma Jr.:
Mixed-mode PISCES-SPICE coupled circuit and device solver. 862-867 - Youn-Long Lin, Daniel D. Gajski:
LES: a layout expert system. 868-876 - Richard I. Hartley, Jeffrey R. Jasica:
Behavioral to structural translation in a bit-serial silicon compiler. 877-886 - Chidchanok Lursinsap, Daniel D. Gajski:
A technique for pull-up transistor folding. 887-896 - Peter M. Maurer, Alexander D. Schapira:
A logic-to-logic comparator for VLSI layout verification. 897-907 - Edmund M. Clarke, Yulin Feng:
Escher-a geometrical layout system for recursively defined circuits. 908-918 - Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront:
On using signature registers as pseudorandom pattern generators in built-in self-testing. 919-928 - Rex E. Lowther:
The solution of a numerical problem encountered when adding a mobility model to a finite-element device simulator. 929-930
Volume 7, Number 9, September 1988
- Sarma Sastry, Melvin A. Breuer:
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences. 933-946 - Wei Shu, Min-You Wu, S. M. Kang:
Improved net merging method for gate matrix layout. 947-951 - Shiuh-Wuu Lee, Robert C. Rennick:
A compact IGFET model-ASIM. 952-975 - Giorgio Casinovi, Alberto L. Sangiovanni-Vincentelli
A new aggregation technique for the solution of large systems of algebraic equations [IC simulation]. 976-986 - Andrew W. Appel
Simulating digital circuits with one bit per wire. 987-993 - Christer Svensson, Robert Tjärnström:
Switch-level simulation and the pass transistor EXOR gate. 994-997 - Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu:
Device and circuit simulation interface for an integrated VLSI design environment. 998-1004 - Silvano Gai, Pier Luca Montessoro, Fabio Somenzi:
MOZART: a concurrent multilevel simulator. 1005-1016 - D. Y. Cheng, Chang G. Hwang, Robert W. Dutton:
PISCES-MC: a multiwindow, multimethod 2-D device simulator. 1017-1026
Volume 7, Number 10, October 1988
- Albertus J. Kemp, Jacobus A. Pretorius, Willem Smit:
The generation of a mesh for resistance calculation in integrated circuits. 1029-1037 - Sepuan Yu, A. F. Franz, T. G. Mihran:
A physical parametric transistor model for CMOS circuit simulation. 1038-1052 - Tian-Shen Tang, M. A. Styblinski:
Yield optimization for nondifferentiable density functions using convolution techniques. 1053-1067 - Laung-Terng Wang, Edward J. McCluskey:
Circuits for pseudoexhaustive test pattern generation. 1068-1080 - Hi-Keung Tony Ma, Srinivas Devadas, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
Test generation for sequential circuits. 1081-1093 - Jason Cong, Martin D. F. Wong
A new approach to three- or four-layer channel routing. 1094-1104 - Micaela Serra, Jon C. Muzio:
Space compaction for multiple-output circuits. 1105-1113 - Fabrizio Lombardi, Donatella Sciuto
An algorithm for functional reconfiguration of fixed-size arrays. 1114-1118 - Wolfgang O. Budde:
Modular testprocessor for VLSI chips and high-density PC boards. 1118-1124
Volume 7, Number 11, November 1988
- Roberto Guerrieri, Alberto L. Sangiovanni-Vincentelli
Three-dimensional capacitance evaluation on a Connection Machine. 1125-1133 - David M. Lewis:
Hardware accelerators for timing simulation of VLSI digital circuits. 1134-1149 - Gen-Lin Tan, Shao-Wei Pan, Walter H. Ku, An-Jui Shey:
ADIC-2.C a general-purpose optimization program suitable for integrated circuit design applications using the pseudo objective function substitution method (POSM). 1150-1163 - Claudio Lombardi, Stefano Manzini, Antonio Saporito, Massimo Vanzi:
A physically based mobility model for numerical simulation of nonplanar devices. 1164-1171 - Paolo Camurati, Paolo Gianoglio, Renato Gianoglio, Paolo Prinetto:
ESTA: an expert system for DFT rule verification. 1172-1180 - F. Joel Ferguson, John Paul Shen:
A CMOS fault extractor for inductive fault analysis. 1181-1194 - Jin-Fuw Lee:
A new framework of design rules for compaction of VLSI layouts. 1195-1204 - Hwan Gue Cho, C. M. Kyung:
A heuristic standard cell placement algorithm using constrained multistage graph model. 1205-1214 - Sharon R. Perkins, Tom Rhyne:
An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function. 1215-1218
Volume 7, Number 12, December 1988
- Zhen-qiu Ning, Patrick M. Dewilde:
SPIDER: capacitance modelling for VLSI interconnections. 1221-1228 - Hiroo Masuda, Yukio Aoki, Jun'ichi Mano, Osamu Yamashiro:
MOSTSM: a physically based charge conservative MOSFET model. 1229-1236 - Lynne Michelle Brocco, Steven Paul McCormick, Jonathan Allen:
Macromodeling CMOS circuits for timing simulation. 1237-1249 - Kewal K. Saluja, Rajiv Sharma, Charles R. Kime:
A concurrent testing technique for digital circuits. 1250-1260 - Y. You, John P. Hayes:
Implementation of VLSI self-testing by regularization. 1261-1271 - Takeshi Tokuda, Jiro Korematsu, Yukihiko Shimazu, Narumi Sakashita, Tohru Kengaku, Toshiki Fugiyama, Takio Ohno, Osamu Tomisawa:
A macrocell approach for VLSI processor design. 1272-1277 - Yen-Tai Lai, Sany M. Leinwand:
Algorithms for floorplan design via rectangular dualization. 1278-1289 - Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
MUSTANG: state assignment of finite state machines targeting multilevel logic implementations. 1290-1300 - Leo R. Piotrowski:
An improved Spice2 Zener diode model for soft-region simulation capability. 1301-1303
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