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VLSI-SoC 2016: Tallinn, Estonia
- 2016 IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016. IEEE 2016, ISBN 978-1-5090-3561-8
- Maede Hemmat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
Hybrid TFET-MOSFET circuits: An approach to design reliable ultra-low power circuits in the presence of process variation. 1-6 - Mohammad Tohidi, Jens Kargaard Madsen, Martijn J. R. Heck, Farshad Moradi
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A low-power analog front-end neural acquisition design for seizure detection. 1-6 - Luca Piccolboni
Stimuli generation through invariant mining for black-box verification. 1-6 - Valerio Tenace
Multi-function logic synthesis of silicon and beyond-silicon ultra-low power pass-gates circuits. 1-6 - Yuan He
Opportunistic circuit-switching for energy efficient on-chip networks. 1-6 - Alejandro Nocua
A Hybrid Power Estimation Technique to improve IP power models quality. 1-6 - Yanzhe Li, Kai Huang, Luc Claesen:
SoC oriented real-time high-quality stereo vision system. 1-6 - Sabyasachee Banerjee
Power-aware test optimization for core-based 3D-SOCs under TSV-constraints. 1-6 - Seyed Saber Nabavi Larimi, Mehdi Kamal, Ali Afzali-Kusha, Hamid Mahmoodi
Power and energy reduction of racetrack-based caches by exploiting shared shift operations. 1-6 - Yukai Chen
Frequency domain characterization of batteries for the design of energy storage subsystems. 1-6 - Seyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi:
Optimistic clock adjustment for preventing Better-than-worst-case violations. 1-6 - Mini Jayakrishnan, Alan Chang, Tae-Hyoung Kim:
Power and area efficient clock stretching and critical path reshaping for error resilience. 1-6 - Boyang Du, Luca Sterpone
An FPGA-based testing platform for the validation of automotive powertrain ECU. 1-7 - Sukarn Agarwal
Restricting writes for energy-efficient hybrid cache in multi-core architectures. 1-6 - Paolo Bernardi
Faster-than-at-speed execution of functional programs: An experimental analysis. 1-6 - Dariusz Obrebski, Cezary Kolacinski
The multi-channel small signal readout system for THz spectroscopy and imaging applications. 1-6 - Guillaume Plassan, Hans-Jörg Peter, Katell Morin-Allory, Fahim Rahim, Shaker Sarwary, Dominique Borrione:
Conclusively verifying clock-domain crossings in very large hardware designs. 1-6 - Charlotte Frenkel
Comparative analysis of redundancy schemes for soft-error detection in low-cost space applications. 1-6 - Lei Wu, Ching-Chuen Jong
A VLSI architecture for real-time gradient guided image filtering. 1-6 - Mahshid Nasserian, Ali Peiravi, Farshad Moradi
A 1.62 µW 8-channel ultra-high input impedance EEG amplifier for dry and non-contact biopotential recording applications. 1-6 - Abhiram Reddy Gundla, Tom Chen:
An efficient multi channel, 425µW QPSK transmitter with tuning for process variation in the Medical Implantable Communications Service (MICS) band of 402-405MHz. 1-5 - Minghao Lin, Heming Sun
Power-efficient and slew-aware three dimensional gated clock tree synthesis. 1-6 - Andreina Zambrano, Hans G. Kerkhoff:
Online digital compensation Method for AMR sensors. 1-6 - Jaehyun Kim, Kiyoung Choi, Sang-Heon Lee, Soojung Ryu:
Dynamic clock synchronization scheme between voltage domains in multi-core architecture. 1-6 - Syed Mohsin Abbas
Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO. 1-5 - Yi Zhao, S. Saqib Khursheed, Bashir M. Al-Hashimi, Zhiwen Zhao:
Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs. 1-6 - Anna Bernasconi, Valentina Ciriani, Luca Frontini
Synthesis on switching lattices of Dimension-reducible Boolean functions. 1-6 - Moritoshi Yasunaga, Naoki Yokoshima, Ikuo Yoshihara:
A passive equalizer and its design methodology for global interconnects in VLSIs. 1-6 - Valentino Peluso
Ultra-Fine Grain Vdd-Hopping for energy-efficient Multi-Processor SoCs. 1-6 - Debjyoti Bhattacharjee
Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays. 1-6 - Motoki Amagasaki, Yuji Nakamura, Takuya Teraoka, Masahiro Iida, Toshinori Sueyoshi:
A novel soft error tolerant FPGA architecture. 1-6 - Xueqing Li, Kaisheng Ma
Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures. 1-6 - Shahzad Muzaffar, Numan Saeed
Automatic protocol configuration in single-channel low-power dynamic signaling for IoT devices. 1-6 - Marcello Traiola
XbarGen: A memristor based boolean logic synthesis tool. 1-6 - Peer Adelt, Bastian Koppelmann, Wolfgang Müller, Markus Becker, Bernd Kleinjohann, Christoph Scheytt
Fast dynamic fault injection for virtual microcontroller platforms. 1-6 - Van-Phuc Hoang
A compact, ultra-low power AES-CCM IP core for wireless body area networks. 1-4 - Jotham Vaddaboina Manoranjan, Solomon Surya Tej Mano Sajjan, Vivek B. Gujari, Kenneth S. Stevens:
Design of a multi-style and multi-frequency FPGA. 1-6 - Erol Koser, Sebastian Krosche, Walter Stechele:
Integrated Soft Error Resilience and Self-Test. 1-6 - Alessandro Bernardini, Wolfgang Ecker, Ulf Schlichtmann
Efficient handling of the fault space in functional safety analysis utilizing formal methods. 1-7 - Wolfgang Ecker, Johannes Schreiner:
Introducing Model-of-Things (MoT) and Model-of-Design (MoD) for simpler and more efficient hardware generators. 1-6 - Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker:
Automatically comparing analog behavior using Earth Mover's Distance. 1-8 - Niklas Krafczyk, Heinz Riener, Görschwin Fey
WCET overapproximation for software in the context of a Cyber-Physical System. 1-6 - Elad Amrani, Avishay Drori, Shahar Kvatinsky:
Logic design with unipolar memristors. 1-5 - Bogdan-Andrei Tabacaru, Moomen Chaari, Wolfgang Ecker, Thomas Kruse, Cristiano Novello:
Speeding up safety verification by fault abstraction and simulation to transaction level. 1-6 - Mengying Zhao, Keni Qiu, Yuan Xie, Jingtong Hu
Redesigning software and systems for non-volatile processors on self-powered devices. 1-6 - Fang Su, Zhibo Wang, Jinyang Li, Meng-Fan Chang, Yongpan Liu:
Design of nonvolatile processors and applications. 1-6 - Shounak Chakraborty, Hemangee K. Kapoor:
Static energy reduction by performance linked dynamic cache resizing. 1-6 - Takashi Nakada, Tomoki Hatanaka, Hiroshi Nakamura
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. 1-7 - Jaan Raik
Foreword. 1
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