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Cyril Chevalier
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2010 – 2019
- 2017
- [j2]Alejandro Nocua
, Arnaud Virazel
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. 26(8): 1740004:1-1740004:19 (2017) - [j1]Alejandro Nocua
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. 13(1): 10-28 (2017) - 2016
- [c7]Alejandro Nocua
A hybrid power modeling approach to enhance high-level power models. DDECS 2016: 151-156 - [c6]Alejandro Nocua
A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC 2016: 1-6 - 2015
- [c5]Alejandro Nocua, Arnaud Virazel
An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM 2015: 17-20 - [c4]Chadi Al Khatib, Claire Aupetit, Cyril Chevalier, Chouki Aktouf, Gilles Sicard, Laurent Fesquet:
A generic clock controller for low power systems: Experimentation on an AXI bus. VLSI-SoC 2015: 307-312 - 2014
- [c3]Chadi Al Khatib, Claire Aupetit, Alejandro Chagoya, Cyril Chevalier, Gilles Sicard, Laurent Fesquet:
Distributed asynchronous controllers for clock management in low power systems. ICECS 2014: 379-382
1990 – 1999
- 1995
- [c2]Christian Dufaza, H. Viallon, Cyril Chevalier:
BIST hardware generator for mixed test scheme. ED&TC 1995: 424-430 - 1993
- [c1]Christian Dufaza, Cyril Chevalier, Lew Fock Chong Lew Yan Voon:
LFSROM an algorithm for automatic design synthesis of hardware test pattern generator. VTS 1993: 208-214
Coauthor Index
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